# US 7,612,580 B2 · Reduced power output buffer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,612,580 B2 - Document ID: US7612580B2 - Status: Granted - Kind: B2 - Application number: 12/070,374 - Filed: 2008-02-15 - Published: 2008-08-28 - Granted: 2009-11-03 - Earliest claimed: 2005-02-28 - Assignees: Silego Technology, Inc. - Inventors: Jie Chen; Ting-Yen Chiang; Kuang-Yu Chen; Chen Yu Wang; Joe Froniewski - Web page: https://patentgrep.com/patent/US7612580B2 ## CPC - H03K 19/018521: {of complementary type, e.g. CMOS} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor. ## Claims ### Claim 1 A clock driving circuit for a PC architecture including: a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances, wherein the output lines are driven differentially at an output voltage lower than a supply voltage; a voltage node having a voltage node impedance, wherein the voltage node is maintained at substantially the output voltage; and a current sinking transistor that sinks current from the voltage node, wherein the current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor; a current sourcing transistor that supplies current to the voltage node, wherein the drain of the current sourcing transistor is maintained at a reference voltage that is lower than the supply voltage; wherein the impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor. ### Claim 2 (depends on 1) A circuit as recited in claim 1, wherein the output lines are driven differentially at approximately 1V or less. ### Claim 3 (depends on 1) A circuit as recited in claim 1, wherein the output buffer includes a plurality of buffers that drive the plurality of output lines. ### Claim 4 (depends on 1) A circuit as recited in claim 1, wherein the linear region is characterized by an approximately linear relationship between the drain to source voltage (VDS) of the current sinking transistor and the drain current (ID) of the current sinking transistor. ### Claim 5 (depends on 1) A circuit as recited in claim 1, wherein the current sourcing transistor acts as a source follower. ### Claim 6 (depends on 1) A circuit as recited in claim 1, wherein the current sourcing transistor is characterized by an ohmic resistance determined by the size of the current sourcing transistor. ### Claim 7 (depends on 1) A circuit as recited in claim 1, wherein the impedance of the voltage node is matched to one of the load impedances by sizing a resistor. ### Claim 8 (depends on 1) A circuit as recited in claim 1, wherein the drain of the current sourcing transistor is connected to a voltage regulator. ### Claim 9 (depends on 1) A circuit as recited in claim 1, wherein the drain of the current sourcing transistor is connected to a voltage divider. ### Claim 10 (depends on 1) A circuit as recited in claim 1, wherein the gate of the current sourcing transistor is maintained at a bias voltage. ### Claim 11 (depends on 1) A circuit as recited in claim 1, wherein the gate of the current sourcing transistor is connected to a voltage regulator. ### Claim 12 (depends on 1) A circuit as recited in claim 1, wherein the gate of the current sourcing transistor is connected to a voltage reference circuit. ### Claim 13 (depends on 1) A circuit as recited in claim 1, wherein the current sourcing transistor is connected to a switch, and wherein the switch is connected to a voltage source. ### Claim 14 (depends on 1) A circuit as recited in claim 1, wherein the current sourcing transistor is connected to a transistor that is configured as a switch to a voltage source. ### Claim 15 (depends on 1) A circuit as recited in claim 1, wherein the current sourcing transistor that supplies current to the voltage node when the current sourcing transistor is turned on; and further including a bleeder network for sinking leakage current from the current sourcing transistor. ### Claim 16 (depends on 1) A circuit as recited in claim 1, further including a bleeder network for sinking leakage current. ### Claim 17 (depends on 1) A circuit as recited in claim 1, further including a bleeder network for sinking leakage current, wherein the bleeder network is connected in parallel with the current sinking transistor. ### Claim 18 (depends on 1) A circuit as recited in claim 1, further including a bleeder network for sinking leakage current, wherein the bleeder network includes a resistor and a transistor. ### Claim 19 (depends on 1) A circuit as recited in claim 1, further including a second current sinking transistor that sinks current from a second voltage node, wherein the second current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the second current sinking transistor. ### Claim 20 (depends on 1) A circuit as recited in claim 1, further including a second current sinking transistor that sinks current from a second voltage node. ### Claim 21 (depends on 1) A circuit as recited in claim 1, further including a second current sinking transistor that sinks leakage current from the current sourcing transistor. ### Claim 22 (depends on 1) A circuit as recited in claim 1, further including a second current sourcing transistor that sources current to a second voltage node maintained at a voltage that is complementary to the output voltage. ### Claim 23 (depends on 1) A circuit as recited in claim 1, wherein the current sourcing transistor acts as a source follower; and further including a second current sinking transistor that sinks current from a second voltage node maintained at a voltage that is complementary to the output voltage; wherein the second current sinking transistor sinks current from the second voltage node and acts as a current source to the current sourcing transistor when the second voltage node is low. ### Claim 24 (depends on 1) A circuit as recited in claim 1, further including a second current sinking transistor that sinks leakage current from the current sourcing transistor, wherein a resistor is connected between the drains of the current sinking transistors. ### Claim 25 (depends on 1) A circuit as recited in claim 1, further including a resistor that sinks leakage current from the current sourcing transistor. ### Claim 26 (depends on 1) A circuit as recited in claim 1, wherein the current sinking transistor is an NMOS transistor. ### Claim 27 (depends on 1) A circuit as recited in claim 1, further including more than one ground pin. ### Claim 28 (depends on 1) A circuit as recited in claim 1, wherein the output buffer includes a first and second buffer, wherein the first buffer is driven by a first clock input and the second buffer is driven by a second clock input that is out of phase with the first clock input. ### Claim 29 A method of driving a plurality of output lines for a PC architecture, including: driving a plurality of output lines differentially at an output voltage lower than a supply voltage, wherein the output lines are connected to a plurality of output loads having output load impedances and wherein the output lines are part of an output buffer for the PC and the output buffer is coupled to a clock generating circuit; maintaining a voltage node at substantially the output voltage, wherein the voltage node has a voltage node impedance; and operating a current sinking transistor in a linear region characterized by an ohmic resistance determined by the size of a current sinking transistor, wherein the current sinking transistor sinks current from the voltage node; maintaining the drain of a current sourcing transistor at a reference voltage that is lower than the supply voltage, wherein the current sourcing transistor supplies current to the voltage node; wherein the impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.