# US 7,612,574 B2 · Systems and methods for defect testing of externally accessible integrated circuit interconnects > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,612,574 B2 - Document ID: US7612574B2 - Status: Granted - Kind: B2 - Application number: 11/627,108 - Filed: 2007-01-25 - Published: 2008-07-31 - Granted: 2009-11-03 - Earliest claimed: 2007-01-25 - Assignees: Micron Technology, Inc. - Inventors: Yoshinori Fujiwara; Masayoshi Nomura - Web page: https://patentgrep.com/patent/US7612574B2 ## CPC - G01R 31/31715: {Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer} - G01R 31/31717: {Interconnect testing (by scan techniques see G01R31/31855)} - G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters - G11C 29/022: {in I/O circuitry} - G11C 29/1201: {comprising I/O circuitry} - G11C 29/56: External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor - G01R 31/3004: {Current or voltage test} - G11C 2029/5006: {Current} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad. ## Claims ### Claim 1 An integrated circuit configurable to permit testing of intended continuity of one or more externally accessible interconnects without contact to the one or more externally accessible interconnects, the integrated circuit comprising: an externally accessible interconnect; an input buffer with an input coupled to the externally accessible interconnect; and a circuit within the integrated circuit that is coupled to the externally accessible interconnect and to the input buffer, wherein in a test mode of operation, the circuit is configured to provide a test signal to the externally accessible interconnect, and wherein in a normal mode of operation, the test signal is not impressed on the externally accessible interconnect. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the circuit comprises at least a multiplexer and an output buffer, wherein the multiplexer is configured to select from an input for the test signal or an input for a normal function, and to provide an output to an input of the output buffer, and wherein the output of the output buffer is coupled to the externally accessible interconnect and to the input buffer. ### Claim 3 (depends on 2) The integrated circuit of claim 2, wherein the circuit is further configured to receive a control signal and the test signal, wherein the multiplexer is controlled by the control signal. ### Claim 4 (depends on 2) The integrated circuit of claim 2, wherein the circuit further comprises a register, wherein an input to the register is coupled to a test signal propagated from another externally accessible interconnect, and wherein an output of the circuit is provided to the multiplexer. ### Claim 5 (depends on 4) The integrated circuit of claim 4, wherein the circuit is further configured to receive a control signal, a clock signal, and the test signal, wherein the multiplexer is controlled by the control signal, and wherein the register is latched by the clock signal. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the circuit comprises at least a switchable device. ### Claim 7 (depends on 6) The integrated circuit of claim 6, wherein the circuit is further configured to receive a control signal and the test signal, wherein the switchable device is controlled by the control signal. ### Claim 8 (depends on 6) The integrated circuit of claim 6, wherein the circuit further comprises a register, wherein the test signal is propagated through the register from a circuit for another externally accessible interconnect, and wherein an output of the register is provided to the multiplexer. ### Claim 9 (depends on 8) The integrated circuit of claim 8, wherein the circuit is further configured to receive a control signal, a clock signal, and the test signal, wherein the switchable device is controlled by the control signal, and wherein the register is latched by the clock signal. ### Claim 10 (depends on 1) The integrated circuit of claim 1, wherein the circuit is further configured to receive the test signal via an externally accessible interconnect and an input buffer other than the externally accessible interconnect and input buffer selected for test. ### Claim 11 (depends on 1) The integrated circuit of claim 1, wherein the externally accessible interconnect comprises a pad. ### Claim 12 (depends on 1) The integrated circuit of claim 1, further comprising memory circuits coupled to the input buffer. ### Claim 13 (depends on 1) The integrated circuit of claim 1, wherein the integrated circuit is further configurable to facilitate test of leakage current of externally accessible interconnects, the integrated circuit further comprising: a second externally accessible interconnect; a first switchable device electrically coupled to the externally accessible interconnect; and a second switchable device electrically coupled to the first switchable device and to the second externally accessible interconnect such that when the first switchable device and the second switchable device are activated during a test mode of operation, a conductive path is formed from the externally accessible interconnect and the second externally accessible interconnect, and wherein in a normal mode of operation, at least one of the first switchable device or the second switchable device is deactivated such that there is no conductive path between the externally accessible interconnect and the second externally accessible interconnect.