# US 7,612,459 B2 · Multi-chip module and single-chip module for chips and proximity connectors

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- Number: US 7,612,459 B2
- Document ID: US7612459B2
- Status: Granted
- Kind: B2
- Application number: 12/117,408
- Filed: 2008-05-08
- Published: 2008-08-28
- Granted: 2009-11-03
- Earliest claimed: 2004-07-26
- Assignees: Sun Microsystems, Inc.
- Inventors: Arthur R. Zingher; Bruce M. Guenin; Edward L. Follmer
- Web page: https://patentgrep.com/patent/US7612459B2

## CPC

- H04B 5/22: Capacitive coupling
- H10W 72/00: Interconnections or connectors in packages
- H10W 90/293: {characterised by non-galvanic coupling between the chips, e.g. capacitive coupling}
- H10W 72/07351: {characterised by changes in properties of the die-attach connectors during connecting}
- H10W 72/30: Die-attach connectors
- H04B: TRANSMISSION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A single-chip module is described. The module includes a first semiconductor die having a first surface and a second surface. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors coupled to the first semiconductor die. A cable coupled to the first semiconductor die is configured to couple power signals to the first semiconductor die. A flexibility compliance of at least one section of the cable is greater than a threshold value thereby allowing the module to be positioned in a mounting structure.

## Claims

### Claim 1

A module, comprising:
a semiconductor die having a first surface and a second surface,
wherein the semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors coupled to the semiconductor die; and
wherein the semiconductor die includes at least three lithographically defined alignment features, the alignment features corresponding to a mounting structure such that the module may be positioned in the mounting structure relative to additional proximity connectors with a deviation in a first dimension in a plane of the first surface of the semiconductor die that is less than one half of a pitch of at least a subset of the plurality of the proximity connectors along the first dimension, and the deviation in a second dimension perpendicular to the plane of the first surface of the semiconductor die that is less than a pre-determined value.

### Claim 2 (depends on 1)

The module of claim 1, wherein the semiconductor die has the plurality of proximity connectors proximate to the first surface and wherein one or more of the plurality of proximity connectors enable communication of data signals by capacitive coupling.

### Claim 3 (depends on 1)

The module of claim 1, wherein one half of the pitch in the first dimension is 25 μm and the pre-determined value is 5 μm.

### Claim 4 (depends on 3)

The module of claim 3, wherein the module may be further positioned in the mounting structure relative to the additional proximity connectors such that the deviation in a third dimension in the plane of the first surface of the semiconductor die is less than one half of the pitch of at least the subset of the plurality of the proximity connectors along the third dimension.

### Claim 5 (depends on 4)

The module of claim 4, wherein one half of the pitch in the third dimension is 25 μm.

### Claim 6 (depends on 1)

The module of claim 1, further comprising a pedestal coupled to the second surface of the semiconductor die via a thermal joint.

### Claim 7 (depends on 6)

The module of claim 6, wherein the thermal joint includes a material selected from the group consisting of solder, a shearable layer of oil, a thermal paste and a coating that reduces static friction.

### Claim 8 (depends on 1)

The module of claim 1, wherein the semiconductor die has substantially symmetric layers deposited on the first surface and the second surface resulting in a substantially 4-fold symmetry that reduces perturbation-induced quadrapole mechanical deviations of the semiconductor die from a plane parallel to the first surface below a pre-determined value.

### Claim 9

A mounting structure for a semiconductor die, comprising:
an opening in the mounting structure configured to receive the semiconductor die, wherein the semiconductor die has a first surface and an a second surface and is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors coupled to the semiconductor die;
at least three lithographically defined alignment features within the opening, the alignment features configured to align with corresponding alignment features on the semiconductor die such that the semiconductor die may be positioned in the mounting structure relative to additional proximity connectors with a deviation in a first dimension in a plane of the first surface of the semiconductor die that is less than one half of a pitch of at least a subset of the plurality of the proximity connectors along the first dimension, and the deviation in a second dimension perpendicular to the plane of the first surface of the semiconductor die that is less than a pre-determined value.

### Claim 10 (depends on 9)

The mounting structure of claim 9, wherein one half of the pitch in the first dimension is 25 μm and the pre-determined value is 5 μm.

### Claim 11 (depends on 9)

The mounting structure of claim 9, wherein the module may be further positioned in the mounting structure relative to the additional proximity connectors such that the deviation in a third dimension in the plane of the first surface of the semiconductor die is less than one half of the pitch of at least the subset of the plurality of the proximity connectors along the third dimension.