# US 7,612,445 B2 · Circuit apparatus and method of fabricating the apparatus

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- Number: US 7,612,445 B2
- Document ID: US7612445B2
- Status: Granted
- Kind: B2
- Application number: 11/740,669
- Filed: 2007-04-26
- Published: 2007-11-01
- Granted: 2009-11-03
- Earliest claimed: 2006-04-27
- Assignees: Sanyo Electric Co., Ltd.
- Inventors: Makoto Murai; Yasuhiro Kohara; Ryosuke Usui
- Web page: https://patentgrep.com/patent/US7612445B2

## CPC

- H05K 3/243: {characterised by selective plating, e.g. for finish plating of pads (selective plating for making the circuit pattern H05K3/108, H05K3/182)}
- H10W 72/00: Interconnections or connectors in packages
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H05K 3/284: {for encapsulating mounted components (H05K1/185 takes precedence)}
- H05K 3/3452: Solder masks
- H05K 3/382: {by special treatment of the metal}
- H05K 2201/0989: Coating free areas, e.g. areas other than pads or lands free of solder resist
- H05K 2203/049: Wire bonding
- H10W 72/07236: {Soldering or alloying}
- H10W 72/075: {of bond wires}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10T 29/49117: Conductor or circuit manufacturing
- Y10T 29/49126: Assembling bases
- Y10T 29/49128: Assembling formed circuit to base
- Y10T 29/49155: Manufacturing circuit on or in base
- Y10T 29/49156: with selective destruction of conductive paths
- Y10T 29/49222: forming array of contacts or terminals
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

The likelihood of exfoliation of a sealing resin layer at a pad electrode part is reduced so that the reliability of a circuit apparatus is improved. A circuit apparatus includes a wiring layer, a gold plating layer, an insulating resin layer, a circuit element, a conductive member and sealing resin layer. The gold plating layer is formed in an wiring layer area for the pad electrode. The surface outside the area is roughened. The insulating resin layer is formed so as to cover the wiring layer and to have an opening in an area in which the pad electrode is formed. The circuit element is mounted on a predetermined area on the insulating resin layer. The sealing resin layer is formed on the insulating resin layer so as to entirely cover the circuit element and the opening for the pad electrode. The sealing resin layer, in the area for the pad electrode, is in contact with the gold plating layer and the wiring layer.

## Claims

### Claim 1

A circuit apparatus comprising:
a substrate;
a copper wiring layer formed on the substrate;
an insulating resin layer formed on the substrate and the wiring layer and having an opening in an area where an electrode pad is formed;
a gold plating layer formed on the electrode pad of the wiring layer surface which is provided in the opening and is used for electrical connection;
a circuit element provided on the substrate;
a conductive member which electrically connects the circuit element and the wiring layer via the gold plating layer; and
a sealing resin layer formed on the insulating resin layer and encapsulating the circuit element and the area where the electrode pad is formed, wherein
the sealing resin layer is in contact with the gold plating layer and the wiring layer.

### Claim 2 (depends on 1)

The circuit apparatus according to claim 1, wherein the circuit element is a semiconductor element.

### Claim 3 (depends on 2)

The circuit apparatus according to claim 2, wherein the semiconductor element is wire bonded using the conductive member.

### Claim 4 (depends on 2)

The circuit apparatus according to claim 2, wherein the semiconductor element is flip chip connected using the conductive member.

### Claim 5 (depends on 1)

The circuit apparatus according to claim 1, wherein the circuit element is a passive element.

### Claim 6 (depends on 1)

The circuit apparatus according to claim 1, wherein the surface of the wiring layer in contact with the sealing resin layer is roughened.

### Claim 7 (depends on 2)

The circuit apparatus according to claim 2, wherein the surface of the wiring layer in contact with the sealing resin layer is roughened.

### Claim 8 (depends on 3)

The circuit apparatus according to claim 3, wherein the surface of the wiring layer in contact with the sealing resin layer is roughened.

### Claim 9 (depends on 4)

The circuit apparatus according to claim 4, wherein the surface of the wiring layer in contact with the sealing resin layer is roughened.

### Claim 10 (depends on 5)

The circuit apparatus according to claim 5, wherein the surface of the wiring layer in contact with the sealing resin layer is roughened.

### Claim 11 (depends on 1)

The circuit apparatus according to claim 1, wherein an area where the sealing resin layer is in contact with the wiring layer is provided around an area where the sealing resin layer is in contact with the gold plating layer.

### Claim 12 (depends on 2)

The circuit apparatus according to claim 2, wherein an area where the sealing resin layer is in contact with the wiring layer is provided around an area where the sealing resin layer is in contact with the gold plating layer.

### Claim 13 (depends on 3)

The circuit apparatus according to claim 3, wherein an area where the sealing resin layer is in contact with the wiring layer is provided around an area where the sealing resin layer is in contact with the gold plating layer.

### Claim 14 (depends on 4)

The circuit apparatus according to claim 4, wherein an area where the sealing resin layer is in contact with the wiring layer is provided around an area where the sealing resin layer is in contact with the gold plating layer.

### Claim 15 (depends on 5)

The circuit apparatus according to claim 5, wherein an area where the sealing resin layer is in contact with the wiring layer is provided around an area where the sealing resin layer is in contact with the gold plating layer.