# US 7,612,439 B2 · Semiconductor package having improved thermal performance

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- Number: US 7,612,439 B2
- Document ID: US7612439B2
- Status: Granted
- Kind: B2
- Application number: 11/316,614
- Filed: 2005-12-22
- Published: 2007-06-28
- Granted: 2009-11-03
- Earliest claimed: 2005-12-22
- Assignees: Alpha and Omega Semiconductor Incorporated
- Inventors: Xiaotian Zhang; Argo Chang; James Lee; Ryan Huang; Kai Liu; Ming Sun
- Web page: https://patentgrep.com/patent/US7612439B2

## CPC

- H10W 90/811: {Multiple chips on leadframes}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 72/07554: {changes in dispositions}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A composite semiconductor package is disclosed. The package includes a lead frame having first and second die bonding pads, the first and second die bonding pads having a large lateral separation therebetween, a first device bonded to the first die bonding pad, a second device bonded to the second die bonding pad, a plurality of first leads coupled to the first die bonding pad, a plurality of second leads coupled to the second die bonding pad, and an encapsulant covering the lead frame, the first and second devices and at least a portion of the first and second pluralities of leads. The package may be a TSSOP-8 composite package having a common drain MOSFET pair and an IC.

## Claims

### Claim 1

A semiconductor package comprising:
a lead frame having first and second die bonding pads, the first and second die bonding pads having a large lateral separation therebetween;
a common drain MOSFET pair banded to the first die bonding pad;
a second device bonded to the second die bonding pad;
a plurality of first leads coupled to the first die bonding pad;
a plurality of second leads coupled to the second die bonding pad; and
an encapsulant covering the lead frame, the first and second devices and at least a portion of the first and second pluralities of leads.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the second device is an IC.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein a portion of the plurality of first leads is fused to the first die bonding pad.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein a lead of the plurality of the second leads is fused to the second die bonding pad.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, further comprising source bonding areas of increased area disposed within the encapsulant.

### Claim 6

A TSSOP-8 composite semiconductor package comprising:
a lead frame;
a common drain MOSFET pair bonded to a first die bonding pad of the lead frame;
an IC bonded to a second die bonding pad of the lead frame;
a first plurality of leads coupled to the first die bonding pad;
a second plurality of leads coupled to the second die bonding pad;
an encapsulant covering the lead frame, the common drain MOSFET pair, the IC and at least a portion of the first and second plurality of leads; and
wherein the first and second die bonding pads are separated a substantial distance laterally one from the other and the encapsulant disposed between the first and second die bonding pads provides for a thermal barrier therebetween.

### Claim 7 (depends on 6)

The TSSOP-8 composite semiconductor package of claim 6, wherein a pair of the first plurality of leads are fused to the first die bonding pad.

### Claim 8 (depends on 6)

The TSSOP-8 composite semiconductor package of claim 6, wherein a lead of the second plurality of lead is fused to the second die bonding pad.

### Claim 9 (depends on 6)

The TSSOP-8 composite semiconductor package of claim 6, further comprising a pair of source bonding areas disposed within the encapsulant, the pair of source bonding areas having an increased area to accommodate an increased number of bonding wires.

### Claim 10

A TSSOP-8 composite semiconductor package comprising:
a lead frame having first and second die bonding pads;
a common drain MOSFET pair bonded to the first die bonding pad;
a second device bonded to the second die bonding pad;
a plurality of first leads coupled to the first die bonding pad, a portion of the plurality of first leads being fused to the first die bonding pad;
a plurality of second leads coupled to the second die bonding pad, a lead of the plurality of the second leads being fused to the second die bonding pad; and
an encapsulant covering the lead frame, the first and second devices and at least a portion of the first and second pluralities of leads.

### Claim 11 (depends on 10)

The TSSOP-8 composite semiconductor package of claim 10, wherein the second device comprises an IC.

### Claim 12 (depends on 10)

The TSSOP-8 composite semiconductor package of claim 10, further comprising a pair of source bonding areas disposed within the encapsulant, the pair of source bonding areas having an increased area to accommodate an increased number of bonding wires.