# US 7,612,435 B2 · Method of packaging integrated circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,612,435 B2 - Document ID: US7612435B2 - Status: Granted - Kind: B2 - Application number: 11/963,388 - Filed: 2007-12-21 - Published: 2009-06-25 - Granted: 2009-11-03 - Earliest claimed: 2007-12-21 - Assignees: National Semiconductor Corporation - Inventors: Jaime A. Bayan; Anindya Poddar - Web page: https://patentgrep.com/patent/US7612435B2 ## CPC - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 70/442: {of multiple leadframes in a single chip} - H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method of packaging an integrated circuit die having a plurality of I/O pads is described. The method includes positioning the die within a die attach area of a first leadframe that includes a plurality of first leads. The method also includes positioning a second leadframe that includes a plurality of second leads over the first leadframe. The method further includes electrically connecting each of the second leads to both an associated I/O pad and a first lead. ## Claims ### Claim 1 An integrated circuit package, comprising: an integrated circuit die, the die having an active surface and a back surface substantially opposite the active surface, the active surface including a plurality of I/O pads; a lower leadframe including a plurality of lower contact leads, each lower contact lead having a first surface and a second surface substantially opposite the first surface, the first surface of each lower contact lead including at least one solder-wettable portion; an upper leadframe including a plurality of metal upper routing leads, each upper routing lead having a first surface and a second surface substantially opposite the first surface, the first surface of each upper routing lead including at least one inner solder-wettable portion and at least one outer solder-wettable portion, each inner solder-wettable portion being physically and electrically connected with an associated I/O pad by an associated solder joint, each outer solder-wettable portion being physically and electrically connected with an associated solder-wettable portion on the first surface of a lower contact lead by an associated solder joint such that each upper routing lead electrically couples an associated I/O pad with an associated lower contact lead, wherein at least most of the first surface of each upper routing lead is in direct contact with the molding material and wherein the first surface of each of the upper routing leads overlies at least most of the first surface of an associated lower contact lead. ### Claim 2 (depends on 1) An integrated circuit package as recited in claim 1, further comprising a molding material that encapsulates portions of the die, lower contact leads and upper routing leads. ### Claim 3 (depends on 2) An integrated circuit package as recited in claim 2, wherein the second surfaces of the upper routing leads are substantially encapsulated with the molding material. ### Claim 4 (depends on 2) An integrated circuit package as recited in claim 2, wherein each second surface of a lower contact lead includes a solder-wettable contact surface that is substantially coplanar with the back surface of the die. ### Claim 5 (depends on 4) An integrated circuit package as recited in claim 4, wherein the solder-wettable contact surfaces and back surface of the die are substantially exposed and un-encapsulated by molding material. ### Claim 6 (depends on 1) An integrated circuit package as recited in claim 1, wherein the first surfaces of the lower contact leads are substantially coplanar with the active surface of the die. ### Claim 7 (depends on 1) An integrated circuit package as recited in claim 1, wherein the lower contact leads are arranged in a quad-flat-pack-no-lead arrangement around the die. ### Claim 8 (depends on 7) An integrated circuit package as recited in claim 7, wherein the upper routing leads are arranged such that each upper routing lead substantially overlies a portion of a corresponding lower contact lead and an associated I/O pad. ### Claim 9 (depends on 7) An integrated circuit package as recited in claim 7, wherein the upper routing leads are arranged into a microarray arrangement, and wherein each upper routing lead substantially overlies a portion of a corresponding lower contact lead and an associated I/O pad. ### Claim 10 (depends on 9) An integrated circuit package as recited in claim 9, wherein each upper routing lead includes a lead trace portion and a contact portion, wherein the contact portion is positioned adjacent the associated I/O pad on the die and wherein at least one lead trace portion extends between contact portions of neighboring upper routing leads. ### Claim 11 (depends on 1) The integrated circuit package as recited in claim 1, wherein a portion of at least one of the upper routing leads is exposed on an exterior surface of the integrated circuit package. ### Claim 12 (depends on 11) The integrated circuit package as recited in claim 11, wherein the lower contact leads and the upper routing leads have substantially the same thickness. ### Claim 13 An arrangement for packaging integrated circuit dice, comprising a first leadframe panel having a multiplicity of first device areas, each first device area having a plurality of first leads, the first leads of each first device area being arranged around an associated die attach area, each of the first leads having a first surface including a first solder pad surface; a multiplicity of integrated circuit dice having a plurality of I/O pads formed thereon, each die being positioned within an associated die attach area; a second leadframe panel having a multiplicity of second device areas, each second device area having a plurality of second leads, each of the second leads having a second surface including an inner second solder pad surface and an outer second solder pad surface, the second leadframe panel being positioned over the first leadframe panel such that the outer second solder pad surfaces are positioned over corresponding first solder pad surfaces of the first leadframe panel and such that the inner second solder pad surfaces are positioned over corresponding I/O pads, wherein the second surface of each of the second leads overlies at least most of the first surface of a corresponding first lead. ### Claim 14 (depends on 13) An arrangement as recited in claim 13, further comprising a plurality of solder joints that physically and electrically connect the inner and outer second solder pad surfaces with the I/O pads and the first solder pad surfaces. ### Claim 15 (depends on 13) The integrated circuit package as recited in claim 13, wherein the second leads are made of metal and wherein at least most of the second surface of each second lead is in direct contact with the molding material. ### Claim 16 (depends on 13) The arrangement as recited in claim 13, wherein ones of the second device areas of the second leadframe panel are coupled with one another using ones of a plurality of tie bars. ### Claim 17 (depends on 16) The arrangement as recited in claim 16, wherein at least one of the second leads and at least one of the first leads have substantially the same width.