# US 7,612,433 B2 · Semiconductor device having self-aligned contact

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- Number: US 7,612,433 B2
- Document ID: US7612433B2
- Status: Granted
- Kind: B2
- Application number: 11/162,725
- Filed: 2005-09-21
- Published: 2006-08-17
- Granted: 2009-11-03
- Earliest claimed: 2005-02-16
- Assignees: Powerchip Semiconductor Corp.
- Inventors: Min-San Huang; Hann-Jye Hsu; Yung-Chung Yao
- Web page: https://patentgrep.com/patent/US7612433B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.

## Claims

### Claim 1

A semiconductor device having self-aligned contacts, comprising:
a substrate;
a plurality of isolation structures, wherein a top of each of the isolation structures keeps a distance to above a top surface of the substrate, and the plurality of the isolation structures is composed of dielectric materials;
a plurality of gate structures, disposed over the substrate;
a plurality of doped areas, disposed in the substrate at each side of the gate structure,
a dielectric layer, covering over the substrate, the isolation structures and the gate structures;
a plurality of conductive plugs, disposed in the dielectric layer and electrically connected with the doped areas;
a plurality of first spacers, disposed on a sidewall of each of the gate structures and between each of the conductive plugs and each of the gate structure; and
a plurality of second spacers, disposed on an entire sidewall surface of each of the isolation structures and between each of the conductive plugs and each of the isolation structures, wherein a material of the second spacers has different etch selection from the isolation structures, wherein the conductive plugs are surrounded by the first spacers and the second spacers.

### Claim 2 (depends on 1)

The semiconductor device having self-aligned contacts of claim 1, wherein the distance between the top of each of the isolation structures and the surface of the substrates is at least 1000 angstroms.

### Claim 3 (depends on 1)

The semiconductor device having self-aligned contacts of claim 1, wherein a material of the first spacers comprises silicon nitride.

### Claim 4 (depends on 1)

The semiconductor device having self-aligned contacts of claim 1, wherein a material of the second spacers comprises silicon nitride.

### Claim 5 (depends on 1)

The semiconductor device having self-aligned contacts of claim 1, wherein a material of the isolation structures comprises silicon oxide.

### Claim 6 (depends on 5)

The semiconductor device having self-aligned contacts of claim 5, wherein the material of the isolation structure comprises silicon oxide of BPSG (borophosphosilicate glass) or TEOS (tetra-ethyl-ortho-silicate).