# US 7,612,421 B2 · Electronic device with dopant diffusion barrier and tunable work function and methods of making same

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- Number: US 7,612,421 B2
- Document ID: US7612421B2
- Status: Granted
- Kind: B2
- Application number: 11/248,633
- Filed: 2005-10-11
- Published: 2007-04-12
- Granted: 2009-11-03
- Earliest claimed: 2005-10-11
- Assignees: Atmel Corporation
- Inventors: Darwin G. Enicks
- Web page: https://patentgrep.com/patent/US7612421B2

## CPC

- H10D 64/01314: {the conductor comprising a layer of Ge, C or of compounds of Si, Ge or C contacting the insulator}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of fabricating a semiconductive film stack for use as a polysilicon germanium gate electrode to address problems associated with implant and diffusion of dopants. Achieving a sufficiently high active dopant concentration at a gate-dielectric interface while avoiding gate penetration of dopants such as boron is problematic. A higher gate implant dosage or annealing temperature is needed, and boron penetration through the thin gate oxide is inevitably enhanced. Both problems are exacerbated as the gate dielectric becomes thinner. In order to achieve a high level of active dopant concentration next to the gate dielectric without experiencing problems associated with gate depletion and penetration, a method and procedures of applying a diffusion-blocking layer is described with respect to an exemplary MOSFET application. However, a diffusion-blocking concept is also presented, which is readily amenable to a variety of semiconductor related technologies.

## Claims

### Claim 1

An electronic device comprising:
a substrate;
a gate dielectric layer disposed over at least a portion of the substrate;
at least one diffusion-blocking layer disposed over at least a portion of the gate dielectric layer, comprised substantially of a first compound semiconductor and including:
an alterable diffusion limiting property which is alterable by doping the first compound semiconductor with one or more diffusion-limiting impurities; and
a first tunable work function which is tunable by doping the first compound semiconductor with one or more additional semiconducting elements or semiconducting compounds; and
at least one main layer comprised substantially of a second compound semiconductor having a second tunable work function, wherein the at least one main layer substantially surrounds the at least one diffusion-blocking layer.

### Claim 2 (depends on 1)

The electronic device of claim 1 wherein the first compound semiconductor is comprised substantially of silicon germanium.

### Claim 3 (depends on 1)

The electronic device of claim 1 wherein the second compound semiconductor is comprised substantially of silicon germanium.

### Claim 4 (depends on 1)

The electronic device of claim 1 wherein between 5% and 100% germanium is incorporated into the at least one diffusion-blocking layer.

### Claim 5 (depends on 1)

The electronic device of claim 1, wherein the at least one diffusion-blocking layer contains a higher level of germanium than the at least one main layer.

### Claim 6 (depends on 1)

The electronic device of claim 1, wherein between 0.1% and 5% carbon is incorporated into the at least one diffusion-blocking layer.

### Claim 7 (depends on 1)

The electronic device of claim 1, wherein the one or more diffusion-limiting impurities are selected from oxygen, fluorine, nitrogen, and combinations thereof.

### Claim 8 (depends on 7)

The electronic device of claim 7, wherein between 0.1% and 10% diffusion-limiting impurities are incorporated into the at least one diffusion-blocking layer.

### Claim 9 (depends on 1)

The electronic device of claim 1, wherein the at least one diffusion-blocking layer is polycrystalline.

### Claim 10 (depends on 1)

The electronic device of claim 1, wherein the at least one diffusion-blocking layer is amorphous.

### Claim 11 (depends on 1)

The electronic device of claim 1, the at least one diffusion-blocking layer has a p-type conductivity.

### Claim 12 (depends on 1)

The electronic device of claim 1, wherein the at least one diffusion-blocking layer has an n-type conductivity.

### Claim 13 (depends on 1)

The electronic device of claim 1, wherein the at least one diffusion-blocking layer further comprises boron, phosphorous, or combinations thereof, in a concentration between 1019 atoms/cm3 and 1021 atoms/cm3.

### Claim 14 (depends on 1)

The electronic device of claim 1 further comprising a liquid crystal display or data storage coupled thereto.

### Claim 15

An electronic device comprising:
a substrate;
a gate dielectric layer disposed over at least a portion of the substrate;
at least one diffusion-blocking layer disposed over at least a portion of the gate dielectric layer, comprised substantially of a first compound semiconductor and including:
an alterable diffusion limiting property which is alterable by doping the first compound semiconductor with one or more diffusion-limiting impurities; and
a first tunable work function which is tunable by doping the first compound semiconductor with one or more additional semiconducting elements or semiconducting compounds; and
at least one main layer is substantially surrounded by the at least one diffusion-blocking layer and comprised substantially of a second compound semiconductor having a second tunable work function.

### Claim 16 (depends on 15)

The electronic device of claim 15 comprising two main layers, wherein a second main layer is located above the at least one diffusion-blocking layer.

### Claim 17 (depends on 15)

The electronic device of claim 15 comprising two diffusion-blocking layers, wherein the at least one main layer is located in between the two diffusion-blocking layers.

### Claim 18 (depends on 15)

The electronic device of claim 15 wherein the first compound semiconductor is comprised substantially of silicon germanium.

### Claim 19 (depends on 15)

The electronic device of claim 15 wherein the second compound semiconductor is comprised substantially of silicon germanium.

### Claim 20 (depends on 15)

The electronic device of claim 15 wherein between 5% and 100% germanium is incorporated into the at least one diffusion-blocking layer.

### Claim 21 (depends on 15)

The electronic device of claim 15, wherein the at least one diffusion-blocking layer contains a higher level of germanium than the at least one main layer.

### Claim 22 (depends on 15)

The electronic device of claim 15, wherein between 0.1% and 5% carbon is incorporated into the at least one diffusion-blocking layer.

### Claim 23 (depends on 15)

The electronic device of claim 15, wherein the one or more diffusion-limiting impurities are selected from oxygen, fluorine, nitrogen, and combinations thereof.

### Claim 24 (depends on 23)

The electronic device of claim 23, wherein between 0.1% and 10% diffusion-limiting impurities are incorporated into the at least one diffusion-blocking layer.

### Claim 25 (depends on 15)

The electronic device of claim 15, wherein the at least one diffusion-blocking layer is polycrystalline.

### Claim 26 (depends on 15)

The electronic device of claim 15, wherein the at least one diffusion-blocking layer is amorphous.

### Claim 27 (depends on 15)

The electronic device of claim 15, the at least one diffusion-blocking layer has a p-type conductivity.

### Claim 28 (depends on 15)

The electronic device of claim 15, wherein the at least one diffusion-blocking layer has an n-type conductivity.

### Claim 29 (depends on 15)

The electronic device of claim 15, wherein the at least one diffusion-blocking layer further comprises boron, phosphorous, or combinations thereof, in a concentration between 1019 atoms/cm3 and 1021 atoms/cm3.

### Claim 30

An integrated circuit structure comprising:
a substrate;
a gate dielectric layer disposed over at least a portion of the substrate;
at least one monocrystalline diffusion-blocking layer disposed over at least a portion of the gate dielectric layer, comprised substantially of a first compound semiconductor and including:
an alterable diffusion limiting property which is alterable by doping the first compound semiconductor with one or more diffusion-limiting impurities; and
a first tunable work function which is tunable by doping the first compound semiconductor with one or more additional semiconducting elements or semiconducting compounds; and
at least one main layer either substantially surrounded by the at least one monocrystalline diffusion-blocking layer or surrounding the at least one monocrystalline diffusion-blocking layer and comprised substantially of a second compound semiconductor having a second tunable work function.

### Claim 31 (depends on 30)

The integrated circuit structure of claim 30 wherein the first compound semiconductor is comprised substantially of silicon germanium.

### Claim 32 (depends on 30)

The integrated circuit structure of claim 30 wherein the second compound semiconductor is comprised substantially of silicon germanium.

### Claim 33 (depends on 30)

The integrated circuit structure of claim 30 wherein between 5% and 100% germanium is incorporated into the at least one monocrystalline diffusion-blocking layer.

### Claim 34

A method of forming an electronic device comprising:
providing a substrate;
forming a gate dielectric layer over at least a portion of the substrate;
forming at least one diffusion-blocking layer disposed over at least a portion of the gate dielectric layer, comprised substantially of a first compound semiconductor having:
an alterable diffusion limiting property which is alterable by doping the first compound semiconductor with one or more diffusion-limiting impurities; and
a first tunable work function which is tunable by doping the first compound semiconductor with one or more additional semiconducting elements or semiconducting compounds; and
forming at least one main layer between the gate dielectric layer and the at least one diffusion-blocking layer, the at least one main layer comprised substantially of a second compound semiconductor having a second tunable work function, wherein the at least one diffusion-blocking layer surrounds the at least one main layer.

### Claim 35 (depends on 34)

The method of claim 34 further comprising in-situ doping of the first and second compound semiconductors.

### Claim 36 (depends on 34)

The method of claim 34 further comprising incorporating arsenic into the at least one diffusion-blocking layer at a concentration of between 1019 atoms/cm3 and 1021 atoms/cm3.

### Claim 37 (depends on 34)

The method of claim 34 further comprising incorporating germanium into the at least one diffusion-blocking layer in a trapezoidal concentration profile, a triangular concentration profile, a box-shape concentration profile, or a semicircular concentration profile.

### Claim 38 (depends on 34)

The method of claim 34 wherein the at least one main layer is comprised substantially of silicon germanium.

### Claim 39 (depends on 38)

The method of claim 38 wherein the concentration of germanium in the at least one main layer is less than a concentration of germanium in the at least one diffusion-blocking layer.

### Claim 40 (depends on 34)

A product formed according to the method of claim 34.