# US 7,612,418 B2 · Monolithic power semiconductor structures including pairs of integrated devices

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- Number: US 7,612,418 B2
- Document ID: US7612418B2
- Status: Granted
- Kind: B2
- Application number: 10/582,035
- Filed: 2004-12-10
- Published: 2007-12-06
- Granted: 2009-11-03
- Earliest claimed: 2003-12-12
- Assignees: Great Wall Semiconductor Corporation
- Inventors: Zheng Shen; David N. Okada
- Web page: https://patentgrep.com/patent/US7612418B2

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 62/314: {having vertical doping variations (vertical IGFETs H10D30/63)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Monolithic semiconductor structures having at least two pairs of two lateral semiconductor devices combined on a first surface of a single semiconductor substrate. Embodiments include connected source terminals defining common source terminals.

## Claims

### Claim 1

A monolithic structure comprising:
a first pair of devices and a second pair of devices, each pair of devices comprising:
a first lateral device having a first source terminal, a first drain terminal, and a first gate terminal, each of said first source, first drain, and first gate terminals terminating on a first surface of a semiconductor substrate, and
a second lateral device having a second source terminal, a second drain terminal and a second gate terminal, each of said second source, second drain, and second gate terminals terminating on said first surface of the semiconductor substrate, and
a multi-layer metal interconnect structure disposed above each pair of devices,
wherein (i) in each pair of devices, said first drain terminal is connected to said second drain terminal via the multi-layer metal interconnect structure, and said first gate terminal is connected to said second gate terminal via the multi-layer metal interconnect structure, (ii) in each pair of devices, each first lateral device is combined with each second lateral device on said substrate, (iii) both first source terminals are connected to both second source terminals to define a common source terminal disposed in the multi-layer metal interconnect structure of the monolithic structure, (iv) the multi-layer metal interconnect structure includes a first electrically isolated lead comprising the common source terminal, (v) said first and second drain terminals of the first pair of devices are electrically independent of the first and second drain terminals of the second pair of devices, and (vi) said first and second gate terminals of the first pair of devices are connected to said first and second drain terminals of the second pair of devices via the multi-layer metal interconnect structure and said first and second gate terminals of the second pair of devices are connected to said first and second drain terminals of the first pair of devices via the multi-layer metal interconnect structure.

### Claim 2

A monolithic structure comprising at least four lateral power transistor devices combined on a semiconductor substrate, said monolithic structure comprising:
a first pair of power transistor devices and a second pair of power transistor devices, each pair of power transistor devices comprising:
a first lateral power transistor device comprising a first source terminal, a first drain terminal and a first gate terminal, each of said first source, first drain, and first gate terminals terminating on a first surface of the semiconductor substrate, and
a second lateral power transistor device comprising a second source terminal, a second drain terminal, and a second gate terminal, each of said second source, second drain, and second gate terminals terminating on said first surface of the semiconductor substrate, and
a multi-layer metal interconnect structure disposed above each pair of devices,
wherein (i) in each pair of devices, said first drain terminal is connected to said second drain terminal via the multi-layer metal interconnect structure, and said first gate terminal is connected to said second gate terminal via the multi-layer metal interconnect structure, (ii) said first and second gate terminals of the first pair of power transistor devices are connected to said first and second drain terminals of the second pair of power transistor devices via the multi-layer metal interconnect structure, (iii) said first and second gate terminals of the second pair of devices are connected to said first and second drain terminals of the first pair of power transistor devices via the multi-layer metal interconnect structure, (iv) said first and second drain terminals of the first pair of devices are electrically independent of the first and second drain terminals of the second pair of power transistor devices, (v) the multi-layer metal interconnect structure includes a first electrically isolated lead comprising both first source terminals-connected to both second source terminals, (vi) the multi-layer metal interconnect structure includes a second electrically isolated lead comprises said first and second drain terminals of the first pair of power transistor devices, and (vii) the multi-layer metal interconnect structure includes a third electrically isolated lead comprising said second drain terminals of the second pair of transistor devices.

### Claim 3 (depends on 2)

The monolithic structure of claim 2 wherein each of said first and second lateral power transistor devices comprises a lateral power MOSFET.

### Claim 4

A monolithic structure comprising at least four lateral power transistor devices combined on a semiconductor substrate, said structure comprising:
a first pair of power transistor devices and a second pair of power transistor devices, each pair of power transistor devices comprising:
a first lateral power transistor device comprising a first source terminal, a first drain terminal, and a first gate terminal, each of said first source, first drain, and first gate terminals terminating on a first surface of the semiconductor substrate, and
a second lateral power transistor device comprising a second source terminal, a second drain terminal, and a second gate terminal, each of said second source, second drain, and second gate terminals terminating on said first surface, and
a multi-layer metal interconnect structure disposed above each pair of devices,
wherein in each pair of devices, said first drain terminal is connected to said second drain terminal via the multi-layer metal interconnect structure and said first gate terminal is connected to said second gate terminal via the multi-layer metal interconnect structure; and the multi-layer metal interconnect structure includes (i) a first electrically isolated lead comprising both first source terminals connected to both second source terminal, (ii) a second electrically isolated lead comprising said first and second drain terminals of the first pair of power transistor devices, (iii) a third electrically isolated lead comprising said first and second drain terminals of the second pair of power transistor devices, and (iv) a fourth electrically isolated lead comprising said first and second gate terminals of the first pair of power transistor devices connected to said first and second gate terminals of the second pair of power transistor devices.

### Claim 5 (depends on 4)

The monolithic structure of claim 4 wherein each of said first and second lateral power transistor devices comprises a lateral power MOSFET.

### Claim 6 (depends on 4)

The monolithic structure of claim 4 wherein a size of said second lateral power transistor is smaller than a size of said first lateral power transistor.

### Claim 7 (depends on 4)

The monolithic structure of claim 4 wherein a first threshold voltage of said first lateral power transistor is different from a second threshold voltage of said second lateral power transistor and a difference in said first and second threshold voltages is at least approximately 0.1 V.

### Claim 8 (depends on 2)

The monolithic structure of claim 2, wherein each of the first and second lateral devices comprise source and drain dopants of a same type.

### Claim 9 (depends on 4)

The monolithic structure of claim 4, wherein each of the first and second lateral devices comprise source and drain dopants of a same type.