# US 7,612,416 B2 · Semiconductor device having a conductive portion below an interlayer insulating film and method for producing the same

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- Number: US 7,612,416 B2
- Document ID: US7612416B2
- Status: Granted
- Kind: B2
- Application number: 10/575,631
- Filed: 2004-09-29
- Published: 2007-06-14
- Granted: 2009-11-03
- Earliest claimed: 2003-10-09
- Assignees: NEC Corporation
- Inventors: Kiyoshi Takeuchi; Koichi Terashima; Hitoshi Wakabayashi; Shigeharu Yamagami; Atsushi Ogura; Masayasu Tanaka; Masahiro Nomura; Koichi Takeda; Toru Tatsumi; Koji Watanabe
- Web page: https://patentgrep.com/patent/US7612416B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/6213: {having rounded corners}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

## Claims

### Claim 1

A semiconductor device comprising:
a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion;
an interlayer insulating film provided on a substrate including the transistor; and
a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor,
wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the buried conductor interconnect is connected to one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film, and has an upper face coplanar with the upper face of the interlayer insulating film and a lower face below the upper face of the semiconductor raised portion at an area of connection with the one of source and drain regions.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the buried conductor interconnect is in contact with opposite side faces of the semiconductor raised portion at an area of connection with the one of source and drain regions.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor device comprises a first transistor and a second transistor as the MIS type field effect transistor, and the buried conductor interconnect is connected to one of source and drain regions of the first transistor and a gate electrode or one of source and drain regions of the second transistor as the another conductive portion.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1 wherein the semiconductor device comprises, as the MIS type field effect transistor, a transistor comprising a plurality of semiconductor raised portions protruding from a substrate plane, a gate electrode formed of a conductor provided over the plurality of semiconductor raised portions and extending from the top to the opposite side faces of each semiconductor raised portion, a gate insulating film existing between the gate electrode and each semiconductor raised portion, and source and drain regions provided in each semiconductor raised portion, and
in the transistor, the buried conductor interconnect is connected to one of source and drain regions of one semiconductor raised portion and one of source and drain regions of another semiconductor raised portion as tic another conductive portion.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein the plurality of semiconductor raised portions are arranged mutually in parallel.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the buried conductor interconnect is connected through a plug or directly to the upper interconnect.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the buried conductor interconnect and one of the source and drain regions are connected through a resistance lowering layer made of a metal or a metallic compound.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor raised portion has a part where width W of the part along a direction parallel to the substrate plane and vertical to the channel length direction is larger than width W of a part below the gate electrode at least at an area of connection between one of the source and drain regions of the semiconductor raised portion and the buried conductor interconnect.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor device comprises, as the MIS type field effect transistor, a first conductivity type transistor and a second conductivity type transistor that constitute a CMOS inverter,
gate electrodes of the first conductivity type transistor and the second conductivity type transistor arc formed of a common conductor, and the conductor is connected to an input node, and
the buried conductor interconnect is connected to. a drain region of the first conductivity type transistor and a drain region of the second conductivity type transistor, and is connected to an output node.

### Claim 11

A semiconductor device comprising a SRAM cell unit having a pair of first and second drive transistors, a pair of first and second load transistors and a pair of first and second transfer transistors, wherein
each of the transistors comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulating film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion;
the semiconductor raised portions of the transistors are arranged with their longitudinal direction extending along a first direction;
the first drive transistor and the first transfer transistor have a common first semiconductor raised portion, the second drive transistor and the second transfer transistor have a common second semiconductor raised portion, the first load transistor has a third semiconductor raised portion adjacent to the first semiconductor raised portion, and the second load transistor has a fourth semiconductor raised portion adjacent to the second semiconductor raised portion; and
the gate electrodes of the first drive transistor and the first load transistor are formed of a common first conductor, the gate electrodes of the second drive transistor and the second load transistor are formed of a common second conductor, and the conductors are arranged with their longitudinal direction extending along a second direction vertical to the first direction;
an interlayer insulating film is provided on a substrate including the SRAM cell unit;
a first buried conductor interconnect is connected to the first conductor, the drain region of the second load transistor, the drain region of the second drive transistor and one of the source and drain regions of the second transfer transistor, and formed on the interlayer. insulating film; and
a second buried conductor interconnect is connected to the second conductor, the drain region of the first load transistor, the drain region of the first drive transistor and one of the source and drain regions of the first transfer transistor, and formed on the interlayer insulating film.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, wherein each of the first and second buried conductor interconnects has an upper face coplanar with the upper face of the interlayer insulating film and a lower face below the upper face of the semiconductor raised portion at areas of connection with the drain regions and the one of source and drain regions.

### Claim 13 (depends on 11)

The semiconductor device according to claim 11, wherein the first and second buried conductor interconnects are in contact with opposite side faces of the semiconductor raised portions at areas of connection with the drain region and the one of source and drain regions.

### Claim 14 (depends on 11)

The semiconductor device according to claim 11 comprising, as the transistor, a transistor comprising a plurality of semiconductor raised portions protruding from a substrate plane, a gate electrode formed of a conductor provided over the plurality of semiconductor raised portions and extending the top to the opposite side faces of each semiconductor raised portion, a gate insulating film existing between the gate electrode and each semiconductor raised portion, and source and drain regions provided in each semiconductor raised portion.