# US 7,612,415 B2 · Method of forming semiconductor device

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- Number: US 7,612,415 B2
- Document ID: US7612415B2
- Status: Granted
- Kind: B2
- Application number: 11/847,052
- Filed: 2007-08-29
- Published: 2008-03-06
- Granted: 2009-11-03
- Earliest claimed: 2006-08-31
- Assignees: Dongbu HiTek Co., Ltd.
- Inventors: Jin-Ha Park
- Web page: https://patentgrep.com/patent/US7612415B2

## CPC

- H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Embodiments relate to a method of forming a 90 nm semiconductor device, including forming an isolation film within a semiconductor substrate in which a pMOS region and an nMOS region are defined. A first mask is formed to shield the nMOS region by using a DUV photoresist having a thickness of approximately 0.7 to 0.75 μm. Ions are implanted into the pMOS region to form a p type well. A second mask is formed to shield the pMOS region by using a DUV photoresist having a thickness of approximately 0.7 to 0.75 μm. Ions are implanted into the nMOS region to form an n type well. A gate oxide film and a gate is formed over the semiconductor substrate. A low-concentration impurity may be implanted by using the gate as a mask. An LDD region may be formed. A sidewall spacer may be formed over both sidewalls of the gate. A high-concentration impurity is implanted by using the sidewall spacer as a mask, forming a source/drain region.

## Claims

### Claim 1

A method comprising:
forming an isolation film within a semiconductor substrate in which a pMOS region and an nMOS region are defined;
forming a first mask to shield an NMOS region by using a deep ultraviolet photoresist having a thickness of approximately 0.7 to 0.75 μm, and implanting ions into the pMOS region to form a p type well;
forming a second mask to shield the pMOS region by using a deep ultraviolet photoresist having a thickness of approximately 0.7 to 0.75 μm, and implanting ions into the nMOS region to form an n type well.

### Claim 2 (depends on 1)

The method of claim 1, wherein the thickness of the deep ultraviolet photoresist is set based on an implant state condition and secondary ion mass spectrometry analysis.

### Claim 3 (depends on 2)

The method of claim 2, wherein the implant state condition includes at least one of a dopant, energy, dose and tilt/twist variation information.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first mask is suitable as a barrier with respect to a dopant 11B+ at an energy of approximately 30 KeV or less.

### Claim 5 (depends on 3)

The method of claim 3, wherein the first mask is used for a pMOS lightly doped drain.

### Claim 6 (depends on 3)

The method of claim 3, wherein a top loss of the photoresist is approximately 250 nm or less.

### Claim 7 (depends on 3)

The method of claim 3, wherein the first mask is suitable as a barrier with respect to a dopant 31P+ at an energy of approximately 30 KeV or less.

### Claim 8 (depends on 3)

The method of claim 3, wherein the first mask is used as an nMOS lightly doped drain.

### Claim 9 (depends on 1)

The method of claim 1, wherein the device method follows 90 nm design rules to form a 90 nm semiconductor device.

### Claim 10 (depends on 1)

The method of claim 1, comprising forming a gate oxide film and a gate over the semiconductor substrate.

### Claim 11 (depends on 10)

The method of claim 10, comprising implanting a low-concentration impurity by using the gate as a mask, forming a lightly doped drain region.

### Claim 12 (depends on 11)

The method of claim 11, comprising forming a sidewall spacer over both sidewalls of the gate.

### Claim 13 (depends on 12)

The method of claim 12, comprising implanting a high-concentration impurity by using the sidewall spacer as a mask, forming a source/drain region.

### Claim 14 (depends on 1)

The method of claim 1, comprising forming a p type field stop layer in the nMOS region.

### Claim 15 (depends on 1)

The method of claim 1, comprising forming an n type field stop layer in the pMOS region.

### Claim 16

An apparatus comprising:
an isolation film formed within a semiconductor substrate in which a pMOS region and an nMOS region are defined;
a p type well formed by implanting ions into the pMOS region after forming a first mask to shield the nMOS region by using a deep ultraviolet photoresist having a thickness of approximately 0.7 to 0.75 μm;
an n type well formed by implanting ions into the NMOS region after forming a second mask to shield the pMOS region by using a deep ultraviolet photoresist having a thickness of approximately 0.7 to 0.75 μm.

### Claim 17 (depends on 16)

The apparatus of claim 16, comprising a gate oxide film and a gate formed over the semiconductor substrate.

### Claim 18 (depends on 17)

The apparatus of claim 17, comprising a lightly doped drain region formed by implanting a low-concentration impurity by using the gate as a mask.

### Claim 19 (depends on 18)

The apparatus of claim 18, comprising a sidewall spacer formed over both sidewalls of the gate.

### Claim 20 (depends on 19)

The apparatus of claim 19, comprising a source/drain region formed by implanting a high-concentration impurity by using the sidewall spacer as a mask.