# US 7,612,412 B2 · Semiconductor device and boost circuit

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- Number: US 7,612,412 B2
- Document ID: US7612412B2
- Status: Granted
- Kind: B2
- Application number: 11/387,227
- Filed: 2006-03-22
- Published: 2006-10-26
- Granted: 2009-11-03
- Earliest claimed: 2005-03-22
- Assignees: Seiko Epson Corporation
- Inventors: Yoshiharu Ajiki
- Web page: https://patentgrep.com/patent/US7612412B2

## CPC

- H10D 84/80: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence)
- H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions}
- H10D 89/215: {comprising arrangements for charge pumping or biasing substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

A semiconductor device, includes: a field-effect transistor that configures a charge-pump circuit; and a supporting substrate that supports the field-effect transistor so that the field-effect transistor provided on the supporting substrate becomes warpable in a channel direction.

## Claims

### Claim 1

A booster circuit, comprising:
a first N-channel field-effect transistor, wherein a first pulse is inputted to a gate;
a first P-channel field-effect transistor that is serially coupled to the first N-channel field-effect transistor, wherein the first pulse is inputted to a gate;
a second N-channel field-effect transistor, wherein a gate is coupled to a drain of the first N-channel field-effect transistor;
a second P-channel field-effect transistor that is serially coupled to the second N-channel field-effect transistor;
a third N-channel field-effect transistor, wherein a second pulse, which has an opposite phase to the first pulse, is inputted to a gate and a source is coupled to a drain of the second N-channel field-effect transistor;
a third P-channel field-effect transistor that is serially coupled to the third N-channel field-effect transistor, wherein a source is coupled to a source of the second N-channel field-effect transistor and the second pulse is inputted to a gate;
a fourth N-channel field-effect transistor wherein a gate is coupled to a drain of the third N-channel field-effect transistor and a source is coupled to a source of the second N-channel field-effect transistor;
a fourth P-channel field-effect transistor that is serially coupled to the fourth N-channel field-effect transistor, wherein: a gate is coupled to a drain of the third P-channel field-effect transistor, a source is coupled to the source of the third P-channel field-effect transistor, and a drain is coupled to a source of the first P-channel field-effect transistor;
a first capacitor that is coupled to the drain of the second N-channel field-effect transistor, whereto the first pulse is inputted;
a second capacitor that is coupled to a drain of the fourth N-channel field-effect transistor, whereto the second pulse is inputted; and
a supporting substrate, on which the first to fourth N-channel field-effect transistors; the first to fourth P-channel field-effect transistors; and the first and second capacitors are provided, that supports the first to fourth N-channel field-effect transistors and the first to fourth P-channel field-effect transistors so that each of the first to fourth N-channel field-effect transistors and the first to fourth P-channel field-effect transistors becomes warpable in a channel direction.

### Claim 2 (depends on 1)

The booster circuit according to claim 1, wherein:
each of the first to fourth N-channel field-effect transistors includes:
a semiconductor layer that is formed on the supporting substrate;
a P-well that is formed on the semiconductor layer;
a first gate electrode that is provided on the P-well;
an N-type source layer that is provided on one side of the first gate electrode and formed on the P-well;
an N-type drain layer that is provided on an other side of the first gate electrode and formed on the P-well; and
a first backgate contact that is provided on the P-well and couples the P-well to the N-type source layer, and
each of the first to fourth P-channel field-effect transistors includes:
a semiconductor layer that is formed on the supporting substrate;
an N-well that is formed on the semiconductor layer;
a second gate electrode that is provided on the N-well;
a P-type source layer that is provided on one side of the second gate electrode and formed on the N-well;
a P-type drain layer that is provided on an other side of the second gate electrode and formed on the N-well; and
a second backgate contact that is provided on the N-well and couples the N-well to the P-type source layer.

### Claim 3 (depends on 1)

The booster circuit according to claim 1, wherein:
lower electrodes of the first and second capacitors are configured of a P-type impurity diffusion layer that configures the sources/drains of the first to fourth P-channel field-effect transistors; and
upper electrodes of the first and second capacitors are configured of a polycrystalline silicon layer that configures the gates of the first to fourth P-channel field-effect transistors.