# US 7,612,406 B2 · Transistor, memory cell array and method of manufacturing a transistor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,612,406 B2 - Document ID: US7612406B2 - Status: Granted - Kind: B2 - Application number: 11/517,557 - Filed: 2006-09-08 - Published: 2008-03-13 - Granted: 2009-11-03 - Earliest claimed: 2006-09-08 - Assignees: Infineon Technologies AG - Inventors: Johannes von Kluge - Web page: https://patentgrep.com/patent/US7612406B2 ## CPC - H10D 64/027: {by etching at gate locations} - H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A transistor includes a first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, the gate groove being defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d1, the depth d1 being measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate. A top surface of the gate electrode is disposed at a depth d2 which is less than the depth d1, the depth d2 being measured from the substrate surface. ## Claims ### Claim 1 An integrated circuit including a transistor, the transistor comprising: first and second source/drain regions formed in a semiconductor material and extending at least to a first depth with respect to a top surface of the semiconductor material; a channel region disposed between the first and second source/drain regions and comprising a fin-like portion including a ridge with a top side and two lateral sides in a cross-section perpendicular to a first direction defined by a line extending between the first and second source/drain regions; and a gate electrode disposed in a gate groove defined in a top surface of the semiconductor material between the first and second source/drain regions; wherein a top surface of the gate electrode is disposed between the top surface of the semiconductor material and the first depth; and wherein the gate electrode surrounds the ridge at the top side and the two lateral sides. ### Claim 2 (depends on 1) The integrated circuit of claim 1, further comprising a spacer comprising a dielectric material, the spacer being disposed adjacent a sidewall of the gate groove and located between the gate electrode and the semiconductor material, wherein a bottom side of the spacer is disposed at a depth no greater than the first depth. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the first source/drain region, the second source/drain region, and the channel region are formed in an active area defined by two opposing isolation trenches, and a width of the ridge is equal to the width of the active area, the width being defined along the first direction. ### Claim 4 (depends on 1) The integrated circuit of claim 1, further comprising at least one vacuum spacer disposed adjacent one of the sidewalls of the gate groove and located between the gate electrode and the semiconductor material, wherein a bottom side of the vacuum spacer is disposed at a depth no greater than the first depth. ### Claim 5 (depends on 4) The integrated circuit of claim 4, wherein a width of the gate groove between a bottom edge of the vacuum spacer and the top surface of the semiconductor material is larger than a width of the gate groove below the bottom edge of the vacuum spacer. ### Claim 6 (depends on 4) The integrated circuit of claim 4, wherein the gate groove has a step at the position of the bottom side of the vacuum spacer. ### Claim 7 An integrated circuit including a memory cell array comprising: a plurality of bit lines extending in a first direction; a plurality of memory cells, each of the memory cells comprising a storage element and an access transistor configured to electrically couple the storage element to one of the bit lines, wherein individual ones of the access transistors are formed in a semiconductor material and comprise: doped portions arranged adjacent a top surface of the semiconductor material and extending to a first depth, wherein the doped portions of each of the access transistors comprise a first source/drain region and a second source/drain region; a channel region formed between the first and second source/drain regions and comprising a fin-like portion including a ridge with a top side and two lateral sides in a cross-section perpendicular to a first direction defined by a line extending between the first and second source/drain regions; and a gate electrode surrounding the ridge at the top side and the two lateral sides; and a plurality of word lines configured to address the access transistors and extending in a second direction intersecting the first direction; wherein a top surface of each of the word lines is disposed at a depth between the top surface of the semiconductor material and the first depth. ### Claim 8 (depends on 7) The integrated circuit of claim 7, wherein a plurality of isolation trenches are formed in the semiconductor material to define active areas between the isolation trenches, wherein the isolation trenches are configured to insulate adjacent active areas from each other, and the access transistors are formed in the active areas. ### Claim 9 (depends on 7) The integrated circuit of claim 7, wherein the storage elements comprise storage capacitors formed in the semiconductor material. ### Claim 10 (depends on 7) The integrated circuit of claim 7, wherein the storage elements comprise storage capacitors formed above the semiconductor material. ### Claim 11 (depends on 7) The integrated circuit of claim 7, wherein the gate electrode forms part of a corresponding word line. ### Claim 12 (depends on 11) The integrated circuit of claim 11, wherein each gate electrode is disposed in a gate groove extending in the top surface of the semiconductor material between the first and the second source/drain regions of each access transistor.