# US 7,612,401 B2 · Non-volatile memory cell

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- Number: US 7,612,401 B2
- Document ID: US7612401B2
- Status: Granted
- Kind: B2
- Application number: 11/338,654
- Filed: 2006-01-25
- Published: 2006-06-22
- Granted: 2009-11-03
- Earliest claimed: 2003-05-27
- Assignees: Kabushiki Kaisha Toshiba
- Inventors: Yoshio Ozawa; Shigehiko Saida; Yuji Takeuchi; Masanobu Saito
- Web page: https://patentgrep.com/patent/US7612401B2

## CPC

- H10B 41/30: characterised by the memory core region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate having at least two isolation trenches that are approximately parallel to each other; and
a non-volatile memory cell provided on the semiconductor substrate,
the non-volatile memory cell comprising:
a tunnel insulating film having a film thickness changing continuously and with three or more periodic, undulating intervals between successive and similar changes in a channel width direction of the non-volatile memory cell, wherein the channel width direction is approximately perpendicular to the isolation trenches;
a floating gate electrode provided on the tunnel insulating film;
a control gate electrode provided above the floating gate electrode; and
an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein a height of an interface between the tunnel insulating film and the semiconductor substrate periodically and continuously changes in the channel width direction.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2,
wherein an upper surface of the tunnel insulating film is nearly flat.

### Claim 4

A semiconductor device comprising:
a semiconductor substrate having at least two isolation trenches that are approximately parallel to each other; and
a non-volatile memory cell provided on the semiconductor substrate,
the non-volatile memory cell comprising:
a tunnel insulating film having an approximately constant film thickness, a height of an interface between the tunnel insulating film and the semiconductor substrate changing continuously and with three or more periodic, undulating intervals between successive and similar changes in a channel width direction of the non-volatile memory cell, wherein the channel width direction is approximately perpendicular to the isolation trenches;
a floating gate electrode provided on the tunnel insulating film, a height of an interface between the floating gate electrode and the tunnel insulating film changing continuously and with three or more periodic, undulating intervals between successive and similar changes in the channel width direction of the non-volatile memory cell;
a control gate electrode above the floating gate electrode; and
an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.