# US 7,612,394 B2 · Thin film transistor array substrate

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- Number: US 7,612,394 B2
- Document ID: US7612394B2
- Status: Granted
- Kind: B2
- Application number: 11/558,451
- Filed: 2006-11-10
- Published: 2007-12-20
- Granted: 2009-11-03
- Earliest claimed: 2006-06-20
- Assignees: Au Optronics Corporation
- Inventors: Wei-Sheng Yu; Chien-Hung Chen
- Web page: https://patentgrep.com/patent/US7612394B2

## CPC

- H10D 86/0231: {using masks, e.g. half-tone masks}
- G02F 1/13458: {Terminal pads}
- G02F 1/136209: {Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making}
- G02F 1/136222: {Colour filters incorporated in the active matrix substrate}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

A thin film transistor array (TFT) substrate and a method for manufacturing the same are provided. The manufacturing method needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost is reduced. In addition, the manufacturing method needs not to form a contact window in a relative thick film layer such as a planarization layer or a color filter layer, so as to connect the pixel electrode to the source/drain, thus the difficulty of the manufacturing process is effectively reduced.

## Claims

### Claim 1

A thin film transistor (TFT) array substrate, comprising:
a substrate;
a patterned composite layer, comprising a first conductive layer, an insulating layer and a channel layer, used to form a plurality of gate lines parallel to each other on the substrate, wherein the insulating layer is located exclusively on the first conductive layer, and the channel layer is formed exclusively on the insulating layer, each of the gate lines has a gate terminal port at a terminal, and the gate terminal port has an opening for exposing the first conductive layer;
a plurality of color filter patterns disposed over the substrate for exposing the composite layer;
a plurality of data lines disposed on the color filter patterns and intersected with the gate lines for forming a plurality of sub-pixel areas on the substrate;
a plurality of pixel electrodes disposed in the corresponding sub-pixel areas and located on the corresponding color filter patterns;
a plurality of sources/drains corresponding to the sub-pixel areas and disposed over the corresponding gate lines to form TFTs with the first conductive layer and the channel layer, wherein the sources/drains are connected to the corresponding data lines and the corresponding pixel electrodes respectively; and
a black matrix disposed over the substrate and exposing the pixel electrodes.

### Claim 2 (depends on 1)

The TFT array substrate of claim 1, further comprising an ohmic contact layer disposed between the channel layer and the sources/drains.

### Claim 3 (depends on 2)

The TFT array substrate of claim 2, further comprising a contact metal layer disposed between the ohmic contact layer and the sources/drains.

### Claim 4 (depends on 1)

The TFT array substrate of claim 1, wherein the composite layer further forms a plurality of common lines parallel to and alternately arranged with the gate lines and the color filter patterns further expose the common lines.

### Claim 5 (depends on 1)

The TFT array substrate of claim 1, further comprising a patterned protective layer disposed between the color filter patterns and the substrate, and between the color filter patterns and the composite layer.

### Claim 6 (depends on 1)

The TFT array substrate of claim 1, wherein the sources/drains are formed by a transparent conductive layer and a second metal layer, and the second metal layer is located on the transparent conductive layer.

### Claim 7 (depends on 6)

The TFT array substrate of claim 6, wherein the pixel electrodes are formed by the transparent conductive layer.

### Claim 8 (depends on 6)

The TFT array substrate of claim 6, further comprising a plurality of gate terminal port contacts disposed on the corresponding gate terminal ports, and respectively coupled to the first conductive layer through the openings.

### Claim 9 (depends on 8)

The TFT array substrate of claim 8, wherein the gate terminal port contacts are formed by the transparent conductive layer.

### Claim 10 (depends on 6)

The TFT array substrate of claim 6, further comprising a plurality of data terminal port contacts connected to terminals of the corresponding data lines.

### Claim 11 (depends on 10)

The TFT array substrate of claim 10, wherein the data terminal port contacts are formed by the transparent conductive layer.