# US 7,612,391 B2 · Semiconductor integrated circuit device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,612,391 B2 - Document ID: US7612391B2 - Status: Granted - Kind: B2 - Application number: 12/236,170 - Filed: 2008-09-23 - Published: 2009-01-29 - Granted: 2009-11-03 - Earliest claimed: 2003-11-13 - Assignees: Renesas Technology Corp. - Inventors: Yusuke Kanno; Hiroyuki Mizuno; Naohiko Irie - Web page: https://patentgrep.com/patent/US7612391B2 ## CPC - G01R 31/318572: {Input/Output interfaces} - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 11/417: for memory cells of the field-effect type - H03K 3/356008: {ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)} - H03K 3/35625: {using complementary field-effect transistors} - H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply} - H10D 84/907: {CMOS gate arrays} - H10D 89/10: Integrated device layouts - H10D 84/85: Complementary IGFETs, e.g. CMOS - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefore for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool. ## Claims ### Claim 1 A semiconductor integrated circuit comprising: a first flip-flop comprising a first latch circuit and a second latch circuit; a first logic circuit connected to an output node of the first flip-flop; a first power line; a second power line; and a third power line, wherein: an output node of the first latch circuit is connected with the output node of the first flip-flop, an input node of the second latch circuit is connected with the output node of the first latch circuit or an input node of the first latch circuit, the first latch circuit and the first logic circuit is supplied with a first operation voltage through the first and the second power line, the second latch circuit is supplied with a second operation voltage through the first and the third power line, a first difference between a width of the first power line and a width of the third power line is larger than a second difference between the width of the third power line and a width of a wiring for connecting the input node of the second latch circuit and the output node or input node of the first latch circuit, a third difference between the width of the second power line and the width of the third power line is larger than the second difference, the third power line has a first state and a second state, and a potential of the third power line in the second state is higher than a potential of the third power line in the first state. ### Claim 2 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein the potential of the third power line in the first state is the same as a potential of the second power line, and the potential of the third power line in the second state is between a potential of the first power line and the second power line. ### Claim 3 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a first mode and a second mode, the first operation voltage is supplied in the first mode, the first operation voltage is cut off and the second operation voltage is supplied in the second mode, and the third power line is controlled to be the second state when the semiconductor integrated circuit is in the second mode. ### Claim 4 (depends on 3) The semiconductor integrated circuit device according to claim 3, further comprising: a first power supply point to supply a potential to the second power line; and a first MISFET including a source-drain path which is provided between the second power line and the first power supply line, wherein the first MISFET is controlled to an ON state in the first mode and the first MISFET is controlled to an OFF state in the second mode. ### Claim 5 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein the first latch circuit includes a second MISFET, the second latch circuit includes a third MISFET, and an absolute value of a threshold voltage of the third MISFET is larger than an absolute value of threshold voltage of the second MISFET. ### Claim 6 (depends on 4) The semiconductor integrated circuit device according to claim 4, wherein the first latch circuit includes a second MISFET, the second latch circuit includes a third MISFET, and an absolute value of a threshold voltage of the first MISFET is larger than an absolute value of threshold voltage of the third MISFET. ### Claim 7 (depends on 3) The semiconductor integrated circuit device according to claim 3, further comprising: a fourth MISFET connecting the second latch circuit with the second power line, wherein the fourth MISFET is turned ON in the first mode and the fourth MISFET is turned OFF in the second mode. ### Claim 8 (depends on 7) The semiconductor integrated circuit device according to claim 7, further comprising: a fifth MISFET connecting the second latch circuit with the third power line, wherein the fifth MISFET is turned OFF in the first mode and the fifth MISFET is turned ON in the second mode. ### Claim 9 (depends on 3) The semiconductor integrated circuit device according to claim 3, wherein the operation voltage supplied to the second latch circuit in the second mode is lower than the operation voltage supplied to the second latch circuit in the first mode. ### Claim 10 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein the second latch circuit includes a capacitive element. ### Claim 11 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein the first logic circuit includes a second MISFET, the second latch circuit includes a third MISFET, and an absolute value of a threshold voltage of the third MISFET is larger than an absolute value of threshold voltage of the second MISFET. ### Claim 12 (depends on 4) The semiconductor integrated circuit device according to claim 4, wherein the first logic circuit includes a second MISFET, the second latch circuit includes a third MISFET, and an absolute value of a threshold voltage of the first MISFET is larger than an absolute value of threshold voltage of the third MISFET.