# US 7,612,389 B2 · Embedded SiGe stressor with tensile strain for NMOS current enhancement

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- Number: US 7,612,389 B2
- Document ID: US7612389B2
- Status: Granted
- Kind: B2
- Application number: 11/227,592
- Filed: 2005-09-15
- Published: 2007-03-15
- Granted: 2009-11-03
- Earliest claimed: 2005-09-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Li-Te S. Lin; Chih-Chien Chang; Tze-Liang Lee
- Web page: https://patentgrep.com/patent/US7612389B2

## CPC

- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the embedded stressor. Preferably, the embedded stressor has a lattice spacing greater than the substrate lattice spacing. In a preferred embodiment, the substrate is silicon and the embedded stressor is silicon germanium. A method of manufacturing is also provided, wherein strained PMOS and NMOS transistors may be formed simultaneously.

## Claims

### Claim 1

A semiconductor device comprising:
a gate electrode formed over a substrate;
a pair of sidewall spacers formed on opposite sides of the gate electrode, wherein the sidewall spacers are in contact with at least a portion of a top surface of a capping layer; and
NMOS source/drain regions formed on either side of the gate electrode,
wherein the NMOS source/drain regions comprise an embedded stressor and a capping layer on the embedded stressor, wherein the embedded stressor has a lattice spacing greater than a substrate lattice spacing and the capping layer has a lattice spacing less than the substrate lattice spacing.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the substrate is silicon and the embedded stressor is silicon germanium.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the capping layer is silicon carbide.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the substrate comprises a material selected from the group consisting essentially of silicon, germanium, silicon germanium, silicon on insulator, silicon germanium on insulator, and combinations thereof.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the capping layer is raised above a surface of the substrate.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the capping layer comprises a material selected from the group consisting essentially of Si, Ge, C, SiC, and combinations thereof.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein at least a portion of the capping layer is located in a recess in the substrate.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the lattice spacing of the embedded stressor is at least about 0.2% greater than the substrate lattice spacing.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the embedded stressor is formed within a recess in the substrate between about 10 nm and about 200 nm deep.

### Claim 10

A structure for straining a channel region of a metal oxide semiconductor (MOS) device comprising:
a substrate having a substrate lattice spacing;
a gate electrode formed over the channel region;
NMOS source/drain regions formed in the substrate oppositely adjacent the gate electrode;
a recess formed in the NMOS source/drain regions;
a first layer formed in the recess, wherein the first layer has a lattice spacing greater than the substrate lattice spacing; and
a second layer formed on the first layer, wherein the second layer has a lattice spacing less than the first layer lattice spacing and wherein the second layer has a lattice spacing less than the substrate lattice spacing; and
a pair of sidewall spacers formed on opposite sides of the gate electrode, wherein a first portion of the sidewall spacers is in contact with at least a corner of a top surface of the second layer.

### Claim 11 (depends on 10)

The structure of claim 10, wherein the substrate is silicon and the first layer is silicon germanium.

### Claim 12 (depends on 10)

The structure of claim 10, wherein the substrate comprises a material selected from the group consisting essentially of silicon, germanium, silicon germanium, silicon on insulator, silicon germanium on insulator, and combinations thereof.

### Claim 13 (depends on 10)

The structure of claim 10, wherein the first layer comprises a material selected from the group consisting essentially of silicon, germanium, silicon germanium, silicon carbide, and combinations thereof.

### Claim 14 (depends on 10)

The structure of claim 10, wherein the second layer comprises a material selected from the group consisting essentially of silicon, germanium, carbon, silicon carbide, and combinations thereof.

### Claim 15 (depends on 10)

The structure of claim 10, wherein the second layer is silicon carbide.

### Claim 16

A semiconductor device comprising:
a gate electrode formed over substrate;
NMOS source/drain regions formed on either side of the gate electrode,
wherein the NMOS source/drain regions comprise an embedded stressor and a capping layer on the embedded stressor, wherein the embedded stressor has a lattice spacing greater than a substrate lattice spacing and the capping layer has a lattice spacing less than the substrate lattice spacing; and
a pair of sidewall spacers formed on opposite sides of the gate electrode, wherein a portion of the sidewall spacers is in contact with the substrate, and a portion of the sidewall spacers contacts at least a portion of a top surface of the capping layer.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the substrate is silicon and the embedded stressor is silicon germanium.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the capping layer is silicon carbide.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein the substrate comprises a material selected from the group consisting essentially of silicon, germanium, silicon germanium, silicon on insulator, silicon germanium on insulator, and combinations thereof.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein the top surface of the capping layer is raised above a surface of the substrate.

### Claim 21 (depends on 16)

The semiconductor device of claim 16, wherein the capping layer comprises a material selected from the group consisting of Si, Ge, C, SiC, and combinations thereof.

### Claim 22 (depends on 16)

The semiconductor device of claim 16, wherein at least a portion of the capping layer is located in a recess in the substrate.

### Claim 23 (depends on 16)

The semiconductor device of claim 16, wherein the lattice spacing of the embedded stressor is at least about 0.2% greater than the substrate lattice spacing.

### Claim 24 (depends on 16)

The semiconductor device of claim 16, wherein the embedded stressor is formed within a recess in the substrate between about 10 nm and about 200 nm deep.