# US 7,612,377 B2 · Thin film transistor array panel with enhanced storage capacitors

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- Number: US 7,612,377 B2
- Document ID: US7612377B2
- Status: Granted
- Kind: B2
- Application number: 11/337,151
- Filed: 2006-01-19
- Published: 2006-08-03
- Granted: 2009-11-03
- Earliest claimed: 2005-01-31
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Kook-Chul Moon; Soong-Yong Joo; Il-Gon Kim; Tae-Hyeong Park
- Web page: https://patentgrep.com/patent/US7612377B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/136213: {Storage capacitors associated with the pixel electrode}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

A thin film transistor array panel is provided. The array panel includes a storage capacitance that is substantially uniform, and allows for a relatively large capacitance in a relatively small area. In some embodiments, the panel includes: a substrate; a plurality of semiconductor regions on the substrate, including a plurality of source and drain regions doped with a first impurity type and a dummy region doped with a second impurity type, and an intrinsic region having storage and channel regions; a gate insulating layer covering at least a portion of the semiconductor regions; a gate line including a gate electrode at least partially overlapping the channel region and formed on the gate insulating layer; a storage line including a storage electrode at least partially overlapping the storage region and formed on the gate insulating layer; a data line including a source electrode connected to the source region and formed on the gate insulating layer; a drain electrode connected to the drain region and the dummy region and formed on the gate insulating layer; and a pixel electrode connected to the drain electrode.

## Claims

### Claim 1

A thin film transistor array panel comprising:
a substrate;
a plurality of semiconductor regions on the substrate, wherein the respective semiconductor regions include a source region and a drain region doped with an N-type impurity, a dummy region doped with a P-type impurity, and intrinsic regions comprising a storage region and a channel region, the storage region being positioned between the drain region and the dummy region;
a gate insulating layer covering at least a portion of the semiconductor regions;
a gate line including a gate electrode and formed on the gate insulating layer, wherein the gate electrode at least partially overlaps the channel region;
a storage line including a storage electrode and formed on the gate insulating layer, wherein the storage electrode at least partially overlaps the storage region;
a data line including a source electrode connected to the source region and formed on the gate insulating layer;
a drain electrode directly contacting both the drain region and the dummy region and formed on the gate insulating layer; and
a pixel electrode connected to the drain electrode.

### Claim 2 (depends on 1)

The thin film transistor array panel of claim 1, wherein the drain electrode at least partially overlaps the storage electrode.

### Claim 3 (depends on 1)

The thin film transistor array panel of claim 1, further comprising: a blocking layer formed between the substrate and the semiconductor regions.

### Claim 4 (depends on 1)

The thin film transistor array panel of claim 1, further comprising:
one or more lightly doped regions disposed between the source and the drain region and the channel region.