# US 7,612,376 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,612,376 B2 - Document ID: US7612376B2 - Status: Granted - Kind: B2 - Application number: 11/459,051 - Filed: 2006-07-21 - Published: 2007-02-15 - Granted: 2009-11-03 - Earliest claimed: 1996-12-27 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Shunpei Yamazaki; Jun Koyama; Hisashi Ohtani - Web page: https://patentgrep.com/patent/US7612376B2 ## CPC - G02F 1/13454: {Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence)} - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - H10D 30/674: {characterised by the active materials} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/40: Crystalline structures - H10D 86/0225: {using crystallisation-promoting species, e.g. using a Ni catalyst} - H10D 86/431: {having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs} - H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics} - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - H10D 86/60: wherein the TFTs are in active matrices - G09G 3/3677: {suitable for active matrices only} - G09G 3/3688: {suitable for active matrices only} - G09G 5/008: {Clock recovery} - G09G 5/18: Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A systemized active matrix display in which a pixel matrix circuit, a driver circuit and a logic circuit are mounted on the same substrate, is formed. A TFT of the present invention has such characteristics as to be able to operate in a wide driving frequency range of 0.05 to 2 GHz, and by designing a channel length and a film thickness of a gate insulating film of the TFT according to characteristics required by circuits, it is possible to form a high frequency driving circuit and a low frequency driving circuit on the same substrate. ## Claims ### Claim 1 A semiconductor device comprising: an N-type thin film transistor having an active layer over a substrate; wherein the active layer comprises a channel region with a channel length of 0.01 to 2 μm; wherein the active layer comprises crystal grain boundaries substantially extending along a channel length direction and existing between top and bottom surfaces of the active layer; and wherein a threshold voltage of the N-type thin film transistor is −0.5 to 15V, the semiconductor device further comprising, over the substrate: a pixel matrix circuit including at least source lines and gate lines; a driver circuit including at least a source line driver circuit for driving the source lines and a gate line driver circuit for driving the gate lines over the substrate; and a logic circuit for processing a signal required for driving the driver circuit and a signal including image information transmitted to the pixel matrix circuit over the substrate. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the logic circuit includes at least one selected from the group consisting of a phase comparator, a low pass filter, a voltage controlled oscillator, a frequency divider, a horizontal scanning oscillator, a vertical scanning oscillator, a D/A converter, an I/O port, a differential amplifier, an operational amplifier, a comparator and a memory. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the active layer comprises a plurality of rod-shaped crystals, and crystal lattices of the plurality of rod-shaped crystals are continuous within each of the active layer. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor device is a liquid crystal display. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the active layer comprises a plurality of rod-shaped crystals, and each of the plurality of rod-shaped crystals has a flattened shape. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the active layer includes an intrinsic or substantially intrinsic channel forming region. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the active layer contains an element selected from the group consisting of Ni, Fe, Co, Sn, Pd, Ph, Pt, Cu and Au at a concentration 1×1017 atoms/cm3 or lower, the element being capable of promoting crystallization of silicon. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the active layer contains an element selected from the group consisting of Cl, F, and Br at a concentration from 1×1015 to 1×1020 atoms/cm3. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the element is concentrated at a portion close to a gate insulating film. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the pixel matrix circuit has a plurality of pixels, and each of the plurality of pixels is provided with at least two thin film transistors connected in series. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the pixel matrix circuit has a plurality of pixels, each of which is provided with a storage capacitor formed between a connect wiring and a black mask. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, further comprising an organic film having an opening wherein the black mask is formed on the organic film and the storage capacitor is formed within the opening. ### Claim 13 A semiconductor device comprising: a P-type thin film transistor having an active layer over a substrate; wherein the active layer comprises a channel region with a channel length of 0.01 to 2 μm; wherein the active layer comprises crystal grain boundaries substantially extending along a channel length direction and existing between top and bottom surfaces of the active layer; and wherein a threshold voltage of the P-type thin film transistor is −1.5 to 0.5V, the semiconductor device further comprising, over the substrate; a pixel matrix circuit including at least source lines and gate lines; a driver circuit including at least a source line driver circuit for driving the source lines and a gate line driver circuit for driving the gate lines over the substrate; and a logic circuit for processing a signal required for driving the driver circuit and a signal including image information transmitted to the pixel matrix circuit over the substrate. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the logic circuit includes at least one selected from the group consisting of a phase comparator, a low pass filter, a voltage controlled oscillator, a frequency divider, a horizontal scanning oscillator, a vertical scanning oscillator, a D/A converter, an I/O port, a differential amplifier, an operational amplifier, a comparator and a memory. ### Claim 15 (depends on 13) The semiconductor device according to claim 13, wherein the active layer comprises a plurality of rod-shaped crystals, and crystal lattices of the plurality of rod-shaped crystals are continuous within each of the active layer. ### Claim 16 (depends on 13) The semiconductor device according to claim 13, wherein the semiconductor device is a liquid crystal display. ### Claim 17 (depends on 13) The semiconductor device according to claim 13, wherein the active layer comprises a plurality of rod-shaped crystals, and each of the plurality of rod-shaped crystals has a flattened shape. ### Claim 18 (depends on 13) The semiconductor device according to claim 13, wherein the active layer includes an intrinsic or substantially intrinsic channel forming region. ### Claim 19 (depends on 13) The semiconductor device according to claim 13, wherein the active layer contains an element selected from the group consisting of Ni, Fe, Co, Sn, Pd, Pb, Pt, Cu and Au at a concentration 1×1017 atoms/cm3 or lower, the element being capable of promoting crystallization of silicon. ### Claim 20 (depends on 13) The semiconductor device according to claim 13, wherein the active layer contains an element selected from the group consisting of Cl, F, and Br at a concentration from 1×1015 to 1×1020 atoms/cm3. ### Claim 21 (depends on 20) The semiconductor device according to claim 20, wherein the element is concentrated at a portion close to a gate insulating film. ### Claim 22 (depends on 13) The semiconductor device according to claim 13, wherein the pixel matrix circuit has a plurality of pixels, and each of the plurality of pixels is provided with at least two thin film transistors connected in series. ### Claim 23 (depends on 13) The semiconductor device according to claim 13, wherein the pixel matrix circuit has a plurality of pixels, each of which is provided with a storage capacitor formed between a connect wiring and a black mask. ### Claim 24 (depends on 23) The semiconductor device according to claim 23, further comprising an organic film having an opening wherein the black mask is formed on the organic film and the storage capacitor is formed within the opening. ### Claim 25 A semiconductor device comprising: a thin film transistor having an active layer over a substrate; wherein the active layer comprises a channel region with a channel length of 0.01 to 2 μm; wherein the active layer comprises crystal grain boundaries substantially extending along a channel length direction and existing between top and bottom surfaces of the active layer; and wherein a subthreshold coefficient of the thin film transistor is 60 to 100 mV/decade, the semiconductor device further comprising, over the substrate; a pixel matrix circuit including at least source lines and gate lines; a driver circuit including at least a source line driver circuit for driving the source lines and a gate line driver circuit for driving the gate lines over the substrate; and a logic circuit for processing a signal required for driving the driver circuit and a signal including image information transmitted to the pixel matrix circuit over the substrate. ### Claim 26 (depends on 25) The semiconductor device according to claim 25, wherein the logic circuit includes at least one selected from the group consisting of a phase comparator, a low pass filter, a voltage controlled oscillator, a frequency divider, a horizontal scanning oscillator, a vertical scanning oscillator, a DIA converter, an I/O port, a differential amplifier, an operational amplifier, a comparator and a memory. ### Claim 27 (depends on 25) The semiconductor device according to claim 25, wherein the active layer comprises a plurality of rod-shaped crystals, and crystal lattices of the plurality of rod-shaped crystals are continuous within each of the active layer. ### Claim 28 (depends on 25) The semiconductor device according to claim 25, wherein the semiconductor device is a liquid crystal display. ### Claim 29 (depends on 25) The semiconductor device according to claim 25, wherein the active layer comprises a plurality of rod-shaped crystals, and each of the plurality of rod-shaped crystals has a flattened shape. ### Claim 30 (depends on 25) The semiconductor device according to claim 25, wherein the active layer includes an intrinsic or substantially intrinsic channel forming region. ### Claim 31 (depends on 25) The semiconductor device according to claim 25, wherein the active layer contains an element selected from the group consisting of Ni, Fe, Co, Sn, Pd, Pb, Pt, Cu and Au at a concentration 1×1017 atoms/cm3 or lower, the element being capable of promoting crystallization of silicon. ### Claim 32 (depends on 25) The semiconductor device according to claim 25, wherein the active layer contains an element selected from the group consisting of Cl, F, and Br at a concentration from 1×1015 to 1×1020 atoms/cm3. ### Claim 33 (depends on 32) The semiconductor device according to claim 32, wherein the element is concentrated at a portion close to a gate insulating film. ### Claim 34 (depends on 25) The semiconductor device according to claim 25, wherein the pixel matrix circuit has a plurality of pixels, and each of the plurality of pixels is provided with at least two thin film transistors connected in series. ### Claim 35 (depends on 25) The semiconductor device according to claim 25, wherein the pixel matrix circuit has a plurality of pixels, each of which is provided with a storage capacitor formed between a connect wiring and a black mask. ### Claim 36 (depends on 25) The semiconductor device according to claim 25, further comprising an organic film having an opening wherein the black mask is formed on the organic film and the storage capacitor is formed within the opening. ### Claim 37 A semiconductor device comprising: an N-type thin film transistor having an active layer over a substrate; wherein the active layer comprises a channel region with a channel length of 0.01 to 2 μm; wherein the active layer comprises crystal grain boundaries substantially extending along a channel length direction and existing between top and bottom surfaces of the active layer; and wherein a field effect mobility of the N-type thin film transistor is 200 to 250 cm2/Vs, the semiconductor device further comprising, over the substrate; a pixel matrix circuit including at least source lines and gate lines; a driver circuit including at least a source line driver circuit for driving the source lines and a gate line driver circuit for driving the gate lines over the substrate; and a logic circuit for processing a signal required for driving the driver circuit and a signal including image information transmitted to the pixel matrix circuit over the substrate. ### Claim 38 (depends on 37) The semiconductor device according to claim 37, wherein the logic circuit includes at least one selected from the group consisting of a phase comparator, a low pass filter, a voltage controlled oscillator, a frequency divider, a horizontal scanning oscillator, a vertical scanning oscillator, a D/A converter, an I/O port, a differential amplifier, an operational amplifier, a comparator and a memory. ### Claim 39 (depends on 37) The semiconductor device according to claim 37, wherein the active layer comprises a plurality of rod-shaped crystals, and crystal lattices of the plurality of rod-shaped crystals are continuous within each of the active layer. ### Claim 40 (depends on 37) The semiconductor device according to claim 37, wherein the semiconductor device is a liquid crystal display. ### Claim 41 (depends on 37) The semiconductor device according to claim 37, wherein the active layer comprises a plurality of rod-shaped crystals, and each of the plurality of rod-shaped crystals has a flattened shape. ### Claim 42 (depends on 37) The semiconductor device according to claim 37, wherein the active layer includes an intrinsic or substantially intrinsic channel forming region. ### Claim 43 (depends on 37) The semiconductor device according to claim 37, wherein the active layer contains an element selected from the group consisting of Ni, Fe, Co, Sn, Pd, Pb, Pt, Cu and Au at a concentration 1×1017 atoms/cm3 or lower, the element being capable of promoting crystallization of silicon. ### Claim 44 (depends on 37) The semiconductor device according to claim 37, wherein the active layer contains an element selected from the group consisting of Cl, F, and Br at a concentration from 1×1015 to 1×1020 atoms/cm3. ### Claim 45 (depends on 44) The semiconductor device according to claim 44, wherein the element is concentrated at a portion close to a gate insulating film. ### Claim 46 (depends on 37) The semiconductor device according to claim 37, wherein the pixel matrix circuit has a plurality of pixels, and each of the plurality of pixels is provided with at least two thin film transistors connected in series. ### Claim 47 (depends on 37) The semiconductor device according to claim 37, wherein the pixel matrix circuit has a plurality of pixels, each of which is provided with a storage capacitor formed between a connect wiring and a black mask. ### Claim 48 (depends on 47) The semiconductor device according to claim 47, further comprising an organic film having an opening wherein the black mask is formed on the organic film and the storage capacitor is formed within the opening. ### Claim 49 A semiconductor device comprising: a P-type thin film transistor having an active layer over a substrate; wherein the active layer comprises a channel region with a channel length of 0.01 to 2 μm; wherein the active layer comprises crystal grain boundaries substantially extending along a channel length direction and existing between top and bottom surfaces of the active layer; and wherein a field effect mobility of the P-type thin film transistor is 150 to 200 cm2/Vs, the semiconductor device further comprising, over the substrate; a pixel matrix circuit including at least source lines and gate lines; a driver circuit including at least a source line driver circuit for driving the source lines and a gate line driver circuit for driving the gate lines over the substrate; and a logic circuit for processing a signal required for driving the driver circuit and a signal including image information transmitted to the pixel matrix circuit over the substrate. ### Claim 50 (depends on 49) The semiconductor device according to claim 49, wherein the logic circuit includes at least one selected from the group consisting of a phase comparator, a low pass filter, a voltage controlled oscillator, a frequency divider, a horizontal scanning oscillator, a vertical scanning oscillator, a D/A converter, an I/O port, a differential amplifier, an operational amplifier, a comparator and a memory. ### Claim 51 (depends on 49) The semiconductor device according to claim 49, wherein the active layer comprises a plurality of rod-shaped crystals, and crystal lattices of the plurality of rod-shaped crystals are continuous within each of the active layer. ### Claim 52 (depends on 49) The semiconductor device according to claim 49, wherein the semiconductor device is a liquid crystal display. ### Claim 53 (depends on 49) The semiconductor device according to claim 49, wherein the active layer comprises a plurality of rod-shaped crystals, and each of the plurality of rod-shaped crystals has a flattened shape. ### Claim 54 (depends on 49) The semiconductor device according to claim 49, wherein the active layer includes an intrinsic or substantially intrinsic channel forming region. ### Claim 55 (depends on 49) The semiconductor device according to claim 49, wherein the active layer contains an element selected from the group consisting of Ni, Fe, Co, Sn, Pd, Pb, Pt, Cu and Au at a concentration 1×1017 atoms/cm3 or lower, the element being capable of promoting crystallization of silicon. ### Claim 56 (depends on 49) The semiconductor device according to claim 49, wherein the active layer contains an element selected from the group consisting of Cl, F, and Br at a concentration from 1×1015 to 1×1020 atoms/cm3. ### Claim 57 (depends on 56) The semiconductor device according to claim 56, wherein the element is concentrated at a portion close to a gate insulating film. ### Claim 58 (depends on 49) The semiconductor device according to claim 49, wherein the pixel matrix circuit has a plurality of pixels, and each of the plurality of pixels is provided with at least two thin film transistors connected in series. ### Claim 59 (depends on 49) The semiconductor device according to claim 49, wherein the pixel matrix circuit has a plurality of pixels, each of which is provided with a storage capacitor formed between a connect wiring and a black mask. ### Claim 60 (depends on 59) The semiconductor device according to claim 59, further comprising an organic film having an opening wherein the black mask is formed on the organic film and the storage capacitor is formed within the opening. ### Claim 61 (depends on 1) The semiconductor device according to claim 1, wherein the crystal grain boundaries of the active layer contact both the top and bottom surfaces of the active layer. ### Claim 62 (depends on 13) The semiconductor device according to claim 13, wherein the crystal grain boundaries of the active layer contact both the top and bottom surfaces of the active layer. ### Claim 63 (depends on 25) The semiconductor device according to claim 25, wherein the crystal grain boundaries of the active layer contact both the top and bottom surfaces of the active layer. ### Claim 64 (depends on 37) The semiconductor device according to claim 37, wherein the crystal grain boundaries of the active layer contact both the top and bottom surfaces of the active layer. ### Claim 65 (depends on 49) The semiconductor device according to claim 49, wherein the crystal grain boundaries of the active layer contact both the top and bottom surfaces of the active layer.