# US 7,612,375 B2 · Semiconductor device and method for fabricating the same

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- Number: US 7,612,375 B2
- Document ID: US7612375B2
- Status: Granted
- Kind: B2
- Application number: 10/421,841
- Filed: 2003-04-24
- Published: 2003-10-30
- Granted: 2009-11-03
- Earliest claimed: 2002-04-24
- Assignees: Sharp Kabushiki Kaisha
- Inventors: Naoki Makita
- Web page: https://patentgrep.com/patent/US7612375B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0225: {using crystallisation-promoting species, e.g. using a Ni catalyst}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/425: {having different crystal properties in different TFTs or within an individual TFT}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes at least one thin-film transistor, which includes a semiconductor layer, a gate electrode and a gate insulating film. In the semiconductor layer, a crystalline region, including a channel forming region, a source region and a drain region, is defined. The gate electrode is provided to control the conductivity of the channel forming region. The gate insulating film is provided between the gate electrode and the semiconductor layer. The semiconductor layer includes a gettering region outside of the crystalline region thereof.

## Claims

### Claim 1

A semiconductor device comprising at least one thin-film transistor, the thin-film transistor including:
a semiconductor layer, including at least one catalytic element for promoting crystallization, in which a crystalline region, including a channel forming region, a source region and a drain region, is defined;
a gate electrode for controlling the conductivity of the channel forming region; and
a gate insulating film, which is provided between the gate electrode and the semiconductor layer, wherein,
when the thin-film transistor operates, the semiconductor layer includes a gettering region having an amorphous phase outside of the crystalline region thereof adjacent to the source region or the drain region,
the at least one catalytic element is included in each of the gettering region, the channel forming region, the source region and the drain region,
a concentration of the at least one catalytic element in the gettering region is higher than the concentration of the at least one catalytic element in each of the channel forming region, the source region and the drain region, individually, and
the at least one catalytic element is selected from the group consisting of Ni, Co, Sn, Pb, Pd, Fe and Cu.

### Claim 2 (depends on 1)

The device of claim 1, wherein the gettering region is partially amorphous.

### Claim 3 (depends on 1)

The device of claim 1, wherein the gettering region is substantially completely amorphous.

### Claim 4 (depends on 1)

The device of claim 1, wherein the percentage of the gettering region that is amorphous is greater than the percentage of the channel forming region that is amorphous, the percentage of the source region that is amorphous and the percentage of the drain region that is amorphous.

### Claim 5 (depends on 1)

The device of claim 1, wherein the semiconductor layer is made of Si, and
wherein the gettering region has a higher Pa/Pc ratio than the channel forming region, where the Pa/Pc ratio is a ratio of a TO phonon peak Pa of amorphous Si to a TO phonon peak Pc of crystalline Si in a Raman spectrum.

### Claim 6 (depends on 5)

The device of claim 5, wherein the gettering region has a higher Pa/Pc ratio than the source region or the drain region.

### Claim 7 (depends on 1)

The device of claim 1, wherein the gettering region is not adjacent to the channel forming region.

### Claim 8 (depends on 1)

The device of claim 1, wherein the gettering region is located outside of a portion of the semiconductor layer, in which an interconnect, connecting respective thin-film transistors together electrically, contacts with the semiconductor layer.

### Claim 9 (depends on 1)

The device of claim 1, wherein the gettering region is located at an outer edge of the semiconductor layer, and
wherein the contact portion between the interconnect and the semiconductor layer overlaps with a portion of the gettering region and a portion of the crystalline region.

### Claim 10 (depends on 1)

The device of claim 1, wherein the gettering region is located at an outer edge of the semiconductor layer, and
wherein the contact portion between the interconnect and the semiconductor layer overlaps with the crystalline region only.

### Claim 11 (depends on 1)

The device of claim 1, wherein multiple thin-film transistors are allocated to the single semiconductor layer and at least two of the thin-film transistors share the source region or the drain region, and
wherein the gettering region is located adjacent to the source region or the drain region that is shared by the at least two thin-film transistors.

### Claim 12 (depends on 1)

The device of claim 1, wherein the gettering regions are provided at the outer edges of the semiconductor layer and between the source regions, between the drain regions or between the source and drain regions, and
wherein the contact portion between the interconnect and the semiconductor layer overlaps with a portion of one of the gettering regions and a portion of the crystalline region.

### Claim 13 (depends on 1)

The device of claim 1, wherein the gettering regions are provided at the outer edges of the semiconductor layer and between the source regions, between the drain regions or between the source and drain regions, and
wherein the contact portion between the interconnect and the semiconductor layer overlaps with the crystalline region only.

### Claim 14

A semiconductor device comprising an n-channel thin-film transistor and a p-channel thin-film transistor,
wherein the n-channel thin-film transistor and the p-channel thin-film transistor each include:
a semiconductor layer, including at least one catalytic element for promoting crystallization, in which a crystalline region, including a channel forming region, a source region and a drain region, is defined;
a semiconductor layer, including at least one catalytic element for promoting crystallization, in which a crystalline region, including a channel forming region, a source region and a drain region, is defined;
a gate electrode for controlling the conductivity of the channel forming region; and
a gate insulating film, which is provided between the gate electrode and the semiconductor layer, wherein,
when the thin-film transistor operates, the semiconductor layer includes a gettering region having an amorphous phase outside of the crystalline region thereof adjacent to the source region or the drain region,
the at least one catalytic element is included in each of the gettering region, the channel forming region, the source region and the drain region,
a concentration of the at least one catalytic element in the gettering region is higher than the concentration of the at least one catalytic element in each of the channel forming region, the source region and the drain region, individually, and
the at least one catalytic element is selected from the group consisting of Ni, Go, Sn, Pb, Pd, Fe and Cu.

### Claim 15 (depends on 14)

The device of claim 14, wherein the gettering region is partially amorphous.

### Claim 16 (depends on 14)

The device of claim 14, wherein the gettering region is substantially completely amorphous.

### Claim 17 (depends on 14)

The device of claim 14, wherein the percentage of the gettering region that is amorphous is greater than the percentage of the channel forming region that is amorphous, the percentage of the source region that is amorphous and the percentage of the drain region that is amorphous.

### Claim 18 (depends on 14)

The device of claim 14, wherein the semiconductor layer is made of Si, and
wherein the gettering region has a higher Pa/Pc ratio than the channel forming region, where the Pa/Pc ratio is a ratio of a TO phonon peak Pa of amorphous Si to a TO phonon peak Pc of crystalline Si in a Raman spectrum.

### Claim 19 (depends on 18)

The device of claim 18, wherein the gettering region has a higher Pa/Pc ratio than the source region or the drain region.

### Claim 20 (depends on 14)

The device of claim 14, wherein the ratio S/W of the area S of the gettering region in the n-channel thin-film transistor to the width W of the channel forming region thereof is approximately equal to the ratio S/W of the area S of the gettering region in the p-channel thin-film transistor to the width W of the channel forming region thereof.

### Claim 21 (depends on 14)

The device of claim 14, wherein a distance L from a junction between the channel forming region and the source region or the drain region to the gettering region in the n-channel thin-film transistor is approximately equal to a distance L from a junction between the channel forming region and the source region or the drain region to the gettering region in the p-channel thin-film transistor.

### Claim 22 (depends on 1, 14)

The device of claim 1 or 14, wherein the gettering region includes an n-type dopant element belonging to Group Vb of the periodic table and a p-type dopant element belonging to Group IIIb of the periodic table.

### Claim 23 (depends on 22)

The device of claim 22, wherein the gettering region includes the n-type dopant element at a concentration of about 1×1019/cm3 to about 1×1021/cm3 and the p-type dopant element at a concentration of about 1.5×1019/cm3 to about 3×1021/cm3.

### Claim 24 (depends on 22)

The device of claim 22, wherein in the gettering region, the concentration of the p-type dopant element is about 1.5 to about 3.0 times as high as that of the n-type dopant element.

### Claim 25 (depends on 1, 14)

The device of claim 1 or 14, wherein the gettering region is doped with at least one rare-gas element that is selected from the group consisting of Ar, Kr and Xe.

### Claim 26 (depends on 25)

The device of claim 25, wherein the gettering region is doped with the rare-gas element at a dose of about 1×1019/cm3 to about 3×1021/cm3.

### Claim 27 (depends on 1, 14)

The device of claim 1 or 14, wherein the gettering region includes the catalytic element at a dose of at least about 1×1019/cm3.

### Claim 28 (depends on 1, 14)

The device of claim 1 or 14, wherein the gate electrode is made of at least one material that is selected from the group consisting of W, Ta, Ti and Mo.

### Claim 29 (depends on 1)

An electronic appliance comprising the semiconductor device of claim 1.

### Claim 30 (depends on 29)

The electronic appliance of claim 29, further comprising a display section that conducts a display operation by using the semiconductor device.