# US 7,612,372 B1 · Method and system for laser thermal processing of semiconductor devices

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- Number: US 7,612,372 B1
- Document ID: US7612372B1
- Status: Granted
- Kind: B1
- Application number: 11/001,906
- Filed: 2004-12-02
- Granted: 2009-11-03
- Earliest claimed: 2003-03-13
- Assignees: Ultratech, Inc.
- Inventors: Yun Wang; Shaoyin Chen
- Web page: https://patentgrep.com/patent/US7612372B1

## CPC

- H10P 30/204: {into Group IV semiconductors}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10P 30/208: {of electrically inactive species}
- H10P 34/42: with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Methods and systems for performing laser thermal processing (LTP) of semiconductor devices are disclosed. The method includes forming a dielectric cap atop a temperature-sensitive element, and then forming an absorber layer atop the dielectric layer. A switch layer may optionally be formed atop the absorber layer. The dielectric cap thermally isolates the temperature-sensitive element from the absorber layer. This allows less-temperature-sensitive regions such as unactivated source and drain regions to be heated sufficiently to activate these regions during LTP via melting and recrystallization of the regions, while simultaneously preventing melting of the temperature-sensitive element, such as a poly-gate.

## Claims

### Claim 1

A system for performing laser thermal processing (LTP) of a semiconductor structure that includes a substrate having a top surface, the system comprising:
an oxide layer and a temperature-sensitive element on said oxide layer formed on a portion of said top surface of the substrate with edges of said oxide layer and temperature-sensitive element substantially in vertical alignment with each other;
a dielectric cap of a first thickness formed atop the temperature-sensitive element with edges of said dielectric cap substantially in vertical alignment with the edges of said temperature sensitive element and said oxide layer forming a three layer stack;
a conformal dielectric barrier layer of a second thickness formed on said substrate top surface and said three layer stack with the combined dielectric layers on said three layer stack having a thickness equal to the sum of said first and second thicknesses; and
an absorber layer formed atop the conformal dielectric barrier layer, wherein during LTP the absorber layer is heated sufficiently for the heat to pass through the second thickness of the conformal dielectric barrier layer to melt a region of the top surface of the substrate and insufficient to pass through the sum of the first and second thicknesses of the combined layers of the dielectric cap and the conformal dielectric barrier layer thus preventing melting of the temperature-sensitive element.

### Claim 2 (depends on 1)

The system of claim 1, wherein:
the temperature-sensitive element is a polysilicon element; and
the region of the top surface of the substrate includes unactivated doped amorphous source and drain regions.

### Claim 3 (depends on 2)

The system of claim 2, wherein the polysilicon element is a poly-gate.

### Claim 4 (depends on 3)

The system of claim 3, wherein the polysilicon element includes at least one of polysilicon runners and polysilicon pads in isolation regions.

### Claim 5 (depends on 1)

The system of claim 1, wherein the dielectric cap has a thickness of between 5 nm and 50 nm.

### Claim 6 (depends on 1)

The system of claim 1, wherein the dielectric cap includes a material selected from the group of materials consisting of: silicon oxide, silicon oxynitride and silicon nitride.

### Claim 7 (depends on 1)

The system of claim 1, wherein the absorber layer includes a metal.

### Claim 8 (depends on 1)

The system of claim 1, further including a switch layer formed atop the absorber layer.

### Claim 9 (depends on 8)

The system of claim 8, wherein the switch layer is a reflectivity-switch layer.

### Claim 10 (depends on 8)

The system of claim 8, wherein the switch layer is a phase-switch layer.

### Claim 11 (depends on 1)

The system of claim 1, wherein the thickness of the dielectric cap is 5 nm to 50 nm and the thickness of the conformal dielectric barrier layer is 5 nm to 15 nm.