# US 7,612,364 B2 · MOS devices with source/drain regions having stressed regions and non-stressed regions

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- Number: US 7,612,364 B2
- Document ID: US7612364B2
- Status: Granted
- Kind: B2
- Application number: 11/602,100
- Filed: 2006-11-20
- Published: 2008-03-06
- Granted: 2009-11-03
- Earliest claimed: 2006-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Harry Chuang; Kong-Beng Thei; Yuan-Chen Sun
- Web page: https://patentgrep.com/patent/US7612364B2

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the stressor comprises an impurity of a first conductivity type; and a portion of the semiconductor substrate adjoining the stressor and on an opposite side of the stressor from the gate stack, wherein the portion of the semiconductor substrate is doped with an impurity of the first conductivity type.

## Claims

### Claim 1

A semiconductor structure comprising:
a semiconductor substrate;
a gate stack on the semiconductor substrate;
a source region comprising:
a first stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack;
a first portion of the semiconductor substrate adjoining the first stressor and on an opposite side of the first stressor from the gate stack; and
a drain region comprising:
a second stressor having at least a portion in the semiconductor substrate and on an opposite side of the gate stack than the first stressor; and
a second portion of the semiconductor substrate adjoining the second stressor and on an opposite side of the second stressor from the gate stack, wherein the first and the second stressors and the first and the second portions of the semiconductor substrate are doped with impurities of a same conductivity type.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1 further comprising a first insulation region in the semiconductor substrate and adjoining the first portion of the semiconductor substrate.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2 further comprising a second insulation region in the semiconductor substrate and adjoining the second portion of the semiconductor substrate.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the conductivity type is p-type, and wherein the first stressor comprises SiGe.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the conductivity type is n-type, and wherein the first stressor comprises SiC.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1 further comprising a silicide film on the first stressor and the first portion of the semiconductor substrate.

### Claim 7

A semiconductor structure comprising:
a semiconductor substrate;
a first metal-oxide-semiconductor (MOS) device comprising:
a first gate stack on the semiconductor substrate;
a first stressor having at least a portion in the semiconductor substrate and adjacent to the first gate stack, wherein the first stressor comprises an impurity of a first conductivity type; and
a first portion of the semiconductor substrate adjoining the first stressor and on an opposite side of the first stressor from the first gate stack, wherein the first portion of the semiconductor substrate is doped with an impurity of the first conductivity type; and
a second MOS device comprising:
a second gate stack on the semiconductor substrate;
a second stressor having at least a portion in the semiconductor substrate and adjacent to the second gate stack, wherein the second stressor comprises an impurity of the first conductivity type; and
a second portion of the semiconductor substrate adjoining the second stressor and on an opposite side of the second stressor from the second gate stack, wherein the second portion of the semiconductor substrate is doped with an impurity of the first conductivity type; and
a third portion of the semiconductor substrate between and adjoining the first and the second portions of the semiconductor substrate.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the third portion of the semiconductor substrate comprises an impurity of the first conductivity type.

### Claim 9 (depends on 7)

The semiconductor structure of claim 7, wherein the third portion of the semiconductor substrate comprises an impurity of a second conductivity type opposite the first conductivity type.

### Claim 10 (depends on 7)

The semiconductor structure of claim 7 further comprising a silicide film on the first stressor and the first portion of the semiconductor substrate.

### Claim 11 (depends on 7)

The semiconductor structure of claim 7, wherein the first conductivity type is p-type, and wherein the first and the second stressors comprise SiGe.

### Claim 12 (depends on 7)

The semiconductor structure of claim 7, wherein the first conductivity type is n-type, and wherein the first and the second stressors comprise SiC.

### Claim 13 (depends on 7)

The semiconductor structure of claim 7, wherein the first MOS device further comprises:
a third stressor having at least a portion in the semiconductor substrate and on an opposite side of the first gate stack from the first stressor, wherein the third stressor comprises an impurity of the first conductivity type; and
an insulation region in the semiconductor substrate and spaced apart from the third stressor by a fourth portion of the semiconductor substrate, wherein the fourth portion of the semiconductor substrate is doped with an impurity of the first conductivity type.

### Claim 14 (depends on 7)

The semiconductor structure of claim 7, wherein a first width of the first stressor and a third width of the third portion of the semiconductor substrate have a first ratio, and wherein a second width of the second stressor and the third width have a second ratio, and wherein each of the first and the second ratios is less than about 0.5.