# US 7,611,979 B2 · Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,611,979 B2
- Document ID: US7611979B2
- Status: Granted
- Kind: B2
- Application number: 11/673,901
- Filed: 2007-02-12
- Published: 2008-08-14
- Granted: 2009-11-03
- Earliest claimed: 2007-02-12
- Assignees: International Business Machines Corporation
- Inventors: Alessandro C. Callegari; Michael P. Chudzik; Barry P. Linder; Renee T. Mo; Vijay Narayanan; Dae-Gyu Park; Vamsi K. Paruchuri; Sufi Zafar
- Web page: https://patentgrep.com/patent/US7611979B2

## CPC

- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 30/0212: {using self-aligned silicidation}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.

## Claims

### Claim 1

A method of forming a multilayered gate stack comprising:
forming a metal nitrogen-containing layer composed of a metal and nitrogen on a surface of a high-k gate dielectric, said metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1, and said metal is selected from Group IVB, VB, VIB and VIIB of the Periodic Table of Elements; and
a forming a Si-containing conductor located directly on a surface of said metal nitrogen-containing layer.

### Claim 2 (depends on 1)

The method of claim 1 wherein said forming said metal nitrogen-containing layer is by sputtering which includes a step of providing a metal target and an atmosphere including argon and nitrogen.

### Claim 3 (depends on 2)

The method of claim 2 wherein said metal target comprises Ti.

### Claim 4 (depends on 1)

The method of claim 1 wherein said compositional ratio is obtained by varying a flow ratio between argon and nitrogen, said argon and nitrogen forming a sputtering atmosphere.

### Claim 5 (depends on 4)

The method of claim 4 wherein said flow ratio between argon and nitrogen is from about 1.0 to 0.1.

### Claim 6 (depends on 5)

The method of claim 5 wherein said flow ratio between argon and nitrogen is 0.75.