# US 7,611,973 B2 · Methods of selectively forming epitaxial semiconductor layer on single crystalline semiconductor and semiconductor devices fabricated using the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,611,973 B2
- Document ID: US7611973B2
- Status: Granted
- Kind: B2
- Application number: 11/154,236
- Filed: 2005-06-16
- Published: 2005-12-22
- Granted: 2009-11-03
- Earliest claimed: 2004-06-17
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Dong-Suk Shin; Hwa-Sung Rhee; Tetsuji Ueno; Ho Lee; Seung-Hwan Lee
- Web page: https://patentgrep.com/patent/US7611973B2

## CPC

- H10D 64/01308: {the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10P 14/2904: {Silicon carbide}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3408: {Silicon carbide}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In methods of selectively forming an epitaxial semiconductor layer on a single crystalline semiconductor and semiconductor devices fabricated using the same, a single crystalline epitaxial semiconductor layer and a non-single crystalline epitaxial semiconductor layer are formed on a single crystalline semiconductor and a non-single crystalline semiconductor pattern respectively, using a main semiconductor source gas and a main etching gas. The non-single crystalline epitaxial semiconductor layer is removed using a selective etching gas. The main gases and the selective etching gas are alternately and repeatedly supplied at least two times to selectively form an elevated single crystalline epitaxial semiconductor layer having a desired thickness only on the single crystalline semiconductor. The selective etching gas suppresses formation of an epitaxial semiconductor layer on the non-single crystalline semiconductor pattern.

## Claims

### Claim 1

A method of fabricating a semiconductor device, comprising:
forming a non-single crystalline semiconductor pattern on a single crystalline semiconductor substrate;
forming an insulating spacer on sidewalls of the non-single crystalline semiconductor pattern;
loading the substrate with the insulating spacer into a reaction chamber;
injecting a main semiconductor source gas and a main etching gas into the reaction chamber to selectively grow a single crystalline epitaxial semiconductor layer on the semiconductor substrate and to selectively grow a non-single crystalline epitaxial semiconductor layer directly on the semiconductor pattern; and
injecting a selective etching gas into the reaction chamber to selectively remove the non-single crystalline epitaxial semiconductor layer selectively grown directly on the semiconductor pattern, wherein the main gases and the selective etching gas are alternately and repeatedly injected at least two times to selectively form an elevated single crystalline semiconductor layer having a desired thickness only on the semiconductor substrate.

### Claim 2 (depends on 1)

The method as recited in claim 1, wherein the single crystalline semiconductor substrate is a single crystalline silicon substrate, a single crystalline germanium substrate, a single crystalline silicon germanium substrate, a single crystalline silicon carbide substrate or a semiconductor on insulator (SOI) substrate including one layer thereof.

### Claim 3 (depends on 1)

The method as recited in claim 1, wherein the non-single crystalline semiconductor pattern is formed of an amorphous semiconductor layer or a polycrystalline semiconductor layer.

### Claim 4 (depends on 1)

The method as recited in claim 1, further comprising:
implanting impurity ions into the single crystalline semiconductor substrate using the non-single crystalline semiconductor pattern and the insulating spacer as ion implantation masks before loading the substrate into the reaction chamber; and
annealing the substrate having the impurity ions to form an activated single crystalline impurity region.

### Claim 5 (depends on 1)

The method as recited in claim 1, further comprising cleaning a surface of the substrate having the insulating spacer before loading the substrate into the reaction chamber.

### Claim 6 (depends on 1)

The method as recited in claim 1 further comprising injecting an in-situ cleaning gas into the reaction chamber before injecting the main semiconductor source gas and the main etching gas.

### Claim 7 (depends on 1)

The method as recited in claim 1, further comprising injecting an initial semiconductor source gas and an initial etching gas into the reaction chamber prior to injection of the main semiconductor source gas and the main etching gas to selectively form an initial single crystalline epitaxial semiconductor layer and an initial non-single crystalline epitaxial semiconductor layer on the semiconductor substrate and the semiconductor pattern respectively, wherein the selective etching gas removes the non-single crystalline epitaxial semiconductor layer and etches the initial non-single crystalline epitaxial semiconductor layer.

### Claim 8 (depends on 1)

The method as recited in claim 1, wherein the main semiconductor source gas is one of a silicon source gas, a germanium source gas, a silicon germanium source gas and a silicon carbide source gas.

### Claim 9 (depends on 1)

The method as recited in claim 1, wherein the main etching gas and the selective etching gas are a gas containing a halogen element which reacts with atoms of the epitaxial semiconductor layers.

### Claim 10 (depends on 1)

The method as recited in claim 1, wherein the main semiconductor source gas and the main etching gas are injected with a dopant gas.

### Claim 11 (depends on 1)

The method as recited in claim 1, further comprising:
injecting a first purge gas into the reaction chamber prior to injection of the selective etching gas; and
injecting a second purge gas into the reaction chamber after injection of the selective etching gas.

### Claim 12 (depends on 3)

The method as recited in claim 3, wherein the amorphous semiconductor layer or the polycrystalline semiconductor layer is formed of a silicon layer, a germanium layer, a silicon germanium layer or a silicon carbide layer.

### Claim 13 (depends on 6)

The method as recited in claim 6, wherein the in-situ cleaning gas is a hydrogen gas.

### Claim 14 (depends on 7)

The method as recited in claim 7, wherein the initial semiconductor source gas and the initial etching gas are injected with a dopant gas.

### Claim 15 (depends on 7)

The method as recited in claim 7, wherein the initial semiconductor source gas is the same gas as the main semiconductor source gas, and the initial etching gas is the same gas as the main etching gas.

### Claim 16 (depends on 8)

The method as recited in claim 8, wherein the silicon source gas is one of a silane (SiH4) gas, a disilane (Si2H6) gas, a dichlorosilane (SiH2Cl2) gas, a SiHCl3 gas and a SiCl4 gas.

### Claim 17 (depends on 8)

The method as recited in claim 8, wherein the germanium source gas is a GeH4 gas.

### Claim 18 (depends on 8)

The method as recited in claim 8, wherein the silicon germanium source gas is a mixture gas of a silicon source gas and a germanium source gas, the silicon source gas being one selected from a group consisting of a silane (SiH4) gas, a disilane (Si2H6) gas, a dichlorosilane (SiH2Cl2) gas, a SiHCl3 gas and a SiCl4 gas, and the germanium source gas being a GeH4 gas.

### Claim 19 (depends on 8)

The method as recited in claim 8, wherein the silicon carbide source gas is a mixture gas of a silicon source gas and a carbon source gas, the silicon source gas being any one selected from a group consisting of a silane (SiH4) gas, a disilane (Si2H6) gas, a dichlorosilane (SiH2Cl2) gas, a SiHCl3 gas and a SiCl4 gas, and the carbon source gas being any one selected from a group consisting of a C2H6 gas and a CH3SiH3 gas.

### Claim 20 (depends on 9)

The method as recited in claim 9, wherein the main etching gas and the selective etching gas are one of a HCl gas, a Cl2 gas and a diluted HCl gas, the diluted HCl gas being a mixture of a HCl gas and a hydrogen gas.

### Claim 21 (depends on 20)

The method as recited in claim 20, wherein the first and second purge gases are a hydrogen gas.

### Claim 22

A method of fabricating a metal oxide semiconductor (MOS) transistor, the method comprising:
forming an isolation layer at a predetermined region of a single crystalline semiconductor substrate to define an active region;
forming an insulated gate electrode on the active region, the gate electrode being formed of a non-single crystalline semiconductor layer;
forming an insulating gate spacer on sidewalls of the non-single crystalline gate electrode;
loading the substrate having the gate spacer into a reaction chamber;
injecting a main semiconductor source gas and a main etching gas into the reaction chamber to selectively form a non-single crystalline epitaxial semiconductor layer on the gate electrode formed of the non-single crystalline semiconductor layer and to selectively form a single crystalline epitaxial semiconductor layer on the active region; and
injecting a selective etching gas into the reaction chamber to selectively remove the non- single crystalline epitaxial semiconductor layer on the gate electrode, wherein the main gases and the selective etching gas are alternately and repeatedly injected at least two times to selectively form elevated single crystalline source/drain regions having a desired thickness only on the active regions adjacent to the gate electrode.

### Claim 23 (depends on 22)

The method as recited in claim 22, wherein the single crystalline semiconductor substrate is a single crystalline silicon substrate, a single crystalline germanium substrate, a single crystalline silicon germanium substrate, a single crystalline silicon carbide substrate or a semiconductor on insulator (SOD substrate having one layer thereof.

### Claim 24 (depends on 22)

The method as recited in claim 22, wherein the non-single crystalline semiconductor layer is formed of an amorphous semiconductor layer or a polycrystalline semiconductor layer.

### Claim 25 (depends on 22)

The method as recited in claim 22, further comprising:
implanting impurity ions into the active region using the gate electrode and the gate spacer as ion implantation masks before loading the substrate into the reaction chamber; and annealing the substrate having the impurity ions to form activated single crystalline source/dram regions.

### Claim 26 (depends on 22)

The method as recited in claim 22 further comprises cleaning a surface of the substrate having the gate spacer before loading the substrate into the reaction chamber.

### Claim 27 (depends on 22)

The method as recited in claim 22 further comprising injecting an in-situ cleaning gas into the reaction chamber prior to injection of the main semiconductor source gas and the main etching gas.

### Claim 28 (depends on 22)

The method as recited in claim 22 further comprising injecting an initial semiconductor source gas and an initial etching gas into the reaction chamber prior to injection of the main semiconductor source gas and the main etching gas to selectively form an initial single crystalline epitaxial semiconductor layer and an initial non-single crystalline epitaxial semiconductor layer on the active region and the gate electrode respectively, wherein the selective etching gas removes of the non-single crystalline epitaxial semiconductor layer and etches the initial non-single crystalline epitaxial semiconductor layer.

### Claim 29 (depends on 22)

The method as recited in claim 22, wherein the main semiconductor source gas is one of a silicon source gas, a germanium source gas, a silicon germanium source gas and a silicon carbide source gas.

### Claim 30 (depends on 22)

The method as recited in claim 22, wherein the main etching gas and the selective etching gas are a gas containing a halogen element which reacts with atoms of the epitaxial semiconductor layers.

### Claim 31 (depends on 22)

The method as recited in claim 22, wherein the main semiconductor source gas and the main etching gas are injected with a dopant gas.

### Claim 32 (depends on 22)

The method as recited in claim 22, further comprising:
injecting a first purge gas into the reaction chamber prior to injection of the selective etching gas; and
injecting a second purge gas into the reaction chamber after injection of the selective etching gas.

### Claim 33 (depends on 22)

The method as recited in claim 22 further comprises selectively forming a metal suicide layer on the gate electrode and the elevated single crystalline source/drain regions.

### Claim 34 (depends on 24)

The method as recited in claim 24, wherein the amorphous semiconductor layer or the polycrystalline semiconductor layer is formed of a silicon layer, a germanium layer, a silicon germanium layer or a silicon carbide layer.

### Claim 35 (depends on 27)

The method as recited in claim 27, wherein the in-situ cleaning gas is a hydrogen gas.

### Claim 36 (depends on 28)

The method as recited in claim 28, wherein the initial semiconductor source gas and the initial etching gas are injected with a dopant gas.

### Claim 37 (depends on 28)

The method as recited in claim 28, wherein the initial semiconductor source gas is the same gas as the main semiconductor source gas, and the initial etching gas is the same gas as the main etching gas.

### Claim 38 (depends on 29)

The method as recited in claim 29, wherein the silicon source gas is one of a silane (SiH4) gas, a disilane (Si2H6) gas, a dichlorosilane (SiH2Cl2) gas, a SiHCl3 gas and a SiCl4 gas.

### Claim 39 (depends on 29)

The method as recited in claim 29, wherein the germanium source gas is a GeH4 gas.

### Claim 40 (depends on 29)

The method as recited in claim 29, wherein the silicon germanium source gas is a mixture gas of a silicon source gas and a germanium source gas, the silicon source gas being one selected from a group consisting of a silane (SiH4) gas, a disilane (Si2H6) gas, a dichlorosilane (SiH2Cl2) gas, a SiHCl3 gas and a SiCl4 gas, and the germanium source gas being a GeH4 gas.

### Claim 41 (depends on 29)

The method as recited in claim 29, wherein the silicon carbide source gas is a mixture gas containing a silicon source gas and a carbon source gas, the silicon source gas being one selected from a group consisting of a silane (SiH4) gas, a disilane (Si2H6) gas, a dichlorosilane (SiH2Cl2) gas, a SiHCl3 gas and a SiCl4 gas, and the carbon source gas being one selected from a group consisting of a C2H6 gas and a CH3SiH3 gas.

### Claim 42 (depends on 30)

The method as recited in claim 30, wherein the main etching gas and the selective etching gas are any one of a HCl gas, a Cl2 gas and a diluted HCl gas, and the diluted HCl gas is a mixture of a HCl gas and a hydrogen gas.

### Claim 43 (depends on 32)

The method as recited in claim 32, wherein the first and second purge gases are a hydrogen gas.