# US 7,611,964 B2 · Method of forming isolation layer of semiconductor memory device

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- Number: US 7,611,964 B2
- Document ID: US7611964B2
- Status: Granted
- Kind: B2
- Application number: 12/163,584
- Filed: 2008-06-27
- Published: 2009-07-02
- Granted: 2009-11-03
- Earliest claimed: 2007-12-28
- Assignees: Hynix Semiconductor Inc.
- Inventors: Jong Hye Cho; Whee Won Cho; Eun Soo Kim
- Web page: https://patentgrep.com/patent/US7611964B2

## CPC

- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10B 41/30: characterised by the memory core region
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present invention relates to a method of forming an isolation layer of a semiconductor memory device. According to a method of fabricating a semiconductor memory device in accordance with an aspect of the present invention, a tunnel insulating layer and a charge trap layer are formed over a semiconductor substrate. An isolation trench is formed by etching the charge trap layer and the tunnel insulating layer. A passivation layer is formed on the entire surface including the isolation trench. A first insulating layer is formed at a bottom of the isolation trench. Portions of the passivation layer, which are oxidized in the formation process of the first insulating layer, are removed. A second insulating layer is formed on the entire surface including the first insulating layer.

## Claims

### Claim 1

A method of fabricating a semiconductor memory device, the method comprising:
forming a tunnel insulating layer and a charge trap layer over a semiconductor substrate;
forming an isolation trench by etching the charge trap layer, the tunnel insulating layer, and the semiconductor substrate;
forming a passivation layer over the charge trap layer and within the isolation trench, the passivation layer coating the isolation trench;
forming a first insulating layer at a bottom portion of the isolation trench, the first insulating layer exposing an portion of the passivation layer, the exposed portion of the passivation layer having been oxidized during the formation of the first insulation layer;
etching the exposed portion of the passivation layer to reduce a thickness of the exposed portion of the passivation layer; and
forming a second insulating layer at least within the isolation trench and over the first insulation layer to form an isolation structure including the first and second insulation layers.

### Claim 2 (depends on 1)

The method of claim 1, wherein a height of the first insulating layer is no more than ½ of a height of the isolation trench.

### Claim 3 (depends on 1)

The method of claim 1, wherein the passivation layer includes nitride.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first insulating layer and the second insulating layer are oxide layers, each formed using a high-density plasma (HDP) process.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first insulating layer is formed using a deposition-etch-deposition (DED) method in which a deposition process, an etch process, and a deposition process are repeated in sequence.

### Claim 6 (depends on 5)

The method of claim 5, wherein the deposition process is performed using a SiH4 gas and an O2 gas.

### Claim 7 (depends on 5)

The method of claim 5, wherein the etch process of the DED method is performed using a remote plasma method employing an NF3 gas.

### Claim 8 (depends on 5)

The method of claim 5, wherein the etch process is performed using an etchant containing NF3 and HF.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
performing an annealing process in oxygen environment after the first insulating layer is formed.

### Claim 10 (depends on 1)

The method of claim 1, wherein the etching of the exposed portion of the passivation layer is performed using an etchant including H2SO4.

### Claim 11 (depends on 1)

The method of claim 1, wherein the passivation layer is formed to a thickness of 200 to 300 angstroms.

### Claim 12

A method of fabricating a semiconductor memory device, the method comprising:
forming a tunnel insulating layer over a semiconductor layer and a charge trap layer over the tunnel insulating layer;
forming an isolation trench by etching the charge trap layer, the tunnel insulating layer, and the semiconductor substrate;
forming a passivation layer on the entire surface including the isolation trench, the passivation layer coating the isolation trench;
forming a first insulating layer within the isolation trench, the first insulating layer filling the a bottom portion of the isolation trench and exposing a portion of the passivation layer that is coating an upper portion of the isolation trench;
partly etching the exposed portion of the passivation layer; and
forming a second insulating layer at least within the isolation trench and over the first insulating layer, wherein the passivation layer formed on sidewalls of the charge trap layer is oxidized during the formation of the second insulating layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the passivation layer includes a nitride layer, wherein the passivation layer is oxidized during the formation of the second insulating layer.

### Claim 14 (depends on 12)

The method of claim 12, wherein the first insulating layer and the second insulating layer each is formed of a high-density plasma (HDP) oxide layer.

### Claim 15 (depends on 12)

The method of claim 12, wherein the first insulating layer is formed using a deposition-etch-deposition (DED) method in which a deposition process, an etch process, and a deposition process are repeated in sequence.

### Claim 16 (depends on 15)

The method of claim 15, wherein the deposition process of the DED method is performed using a SiH4 gas and an O2 gas.

### Claim 17 (depends on 15)

The method of claim 15, wherein the etch process of the DED method is performed using a remote plasma method employing an NF3 gas or an etchant containing NF3 and HF.

### Claim 18 (depends on 12)

The method of claim 12, further comprising:
after the first insulating layer is formed, performing an annealing process employing an oxygen gas.

### Claim 19 (depends on 1)

The method of claim 1, wherein the exposed portion of the passivation layer is etched using an etchant containing H2SO4.

### Claim 20 (depends on 12)

The method of claim 12, wherein the passivation layer is formed to a thickness of 200 to 300 angstroms.