# US 7,611,957 B2 · Method of manufacturing semiconductor device

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- Number: US 7,611,957 B2
- Document ID: US7611957B2
- Status: Granted
- Kind: B2
- Application number: 11/699,584
- Filed: 2007-01-30
- Published: 2007-08-02
- Granted: 2009-11-03
- Earliest claimed: 2006-01-30
- Assignees: Sanyo Electric Co., Ltd.
- Inventors: Eiji Nishibe; Toshihiro Hachiyanagi
- Web page: https://patentgrep.com/patent/US7611957B2

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 1/47: Resistors having no potential barriers
- H10D 84/817: {Combinations of field-effect devices and resistors only}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The invention provides a method of manufacturing a semiconductor device having a semiconductor resistor layer, which reduces a difference between a theoretical resistance value and a measured resistance value. An interlayer insulation film is formed on the whole surface of a semiconductor substrate, and then the interlayer insulation film is selectively etched to form contact holes partially exposing a polysilicon resistor layer, a source region and a drain region. The patterning size of the polysilicon resistor layer is designed by defining the lengths between the adjacent contact holes on the polysilicon resistor layer as the lengths of resistor elements. Then, ion implantation is performed to the polysilicon resistor layer through the contact holes to form low resistance regions (regions where high concentration of impurities are implanted) on the polysilicon resistor layer. After the ion implantation, heat treatment (annealing) is performed at lower temperature than in heat treatment for forming the source region and the drain region.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate;
forming an element separation insulation film on the substrate;
forming a gate insulation film on the substrate;
forming a semiconductor resistor layer on the element separation insulation film;
forming a gate electrode on the gate insulation film;
performing a first ion implantation into the substrate so as to form a source region and a drain region adjacent the gate electrode;
performing a first heat treatment to activate the source and drain regions after the first ion implantation;
forming an interlayer insulation film having contact holes exposing part of the semiconductor resistor layer, part of the source region and part of the drain region;
performing, after the first heat treatment, a second ion implantation into the semiconductor resistor layer through the contact holes to form low resistance regions in the semiconductor layer for electrical contact; and
performing a second heat treatment to activate ions implanted in the second ion implantation at a temperature lower than in the first heat treatment.

### Claim 2 (depends on 1)

The method of claim 1, wherein the semiconductor resistor layer comprises a polysilicon layer.