# US 7,611,956 B2 · Semiconductor device having MOS varactor and methods for fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,611,956 B2 - Document ID: US7611956B2 - Status: Granted - Kind: B2 - Application number: 11/941,192 - Filed: 2007-11-16 - Published: 2008-04-03 - Granted: 2009-11-03 - Earliest claimed: 2004-02-12 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Dae-Hyun Kim; Han-Su Oh - Web page: https://patentgrep.com/patent/US7611956B2 ## CPC - H10D 84/215: {of only varactors} - H10D 1/64: Variable-capacitance diodes, e.g. varactors - H10D 1/66: Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors - H10D 84/217: {of only conductor-insulator-semiconductor capacitors} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device with having a MOS varactor and methods of fabricating the same are disclosed. The MOS varactor includes a metal gate electrode, an active semiconductor plate interposed between the metal gate electrode and the semiconductor substrate, and a capacitor dielectric layer interposed between the metal gate electrode and the active semiconductor plate. Further, a lower insulating layer insulates the MOS varactor from the semiconductor substrate. According to the present invention, a metal gate electrode is used to reduce poly depletion, thereby increasing a tuning range of the varactor, and to manufacture a reliable metal resistor without the need of an additional photomask. ## Claims ### Claim 1 A method for fabricating a semiconductor device, the method comprising: forming a lower insulating layer on a semiconductor substrate; forming a lightly doped semiconductor layer on the lower insulating layer; sequentially forming a dielectric layer and a metal layer on the lightly doped semiconductor layer; forming a metal gate electrode, a capacitor dielectric layer, and an active semiconductor plate having extended portions by patterning the metal layer, the dielectric layer, and the lightly doped semiconductor layer within a first region of the lower insulating layer; forming a metal resistor on the same plane as the metal gate electrode by patterning the metal layer within a second region of the lower insulating layer at the same time the metal layer, the dielectric layer, and the lightly doped semiconductor layer within the first region of the lower insulating layer are patterned; and forming highly doped regions within the active semiconductor plate by implanting impurity ions into the active semiconductor plate, using the metal gate electrode as an ion implantation mask. ### Claim 2 (depends on 1) The method as claimed in claim 1, further comprising forming a semiconductor resistor by patterning the dielectric layer and the lightly doped semiconductor layer within the second region of the lower insulating layer while patterning the metal layer, the dielectric layer, and the lightly doped semiconductor layer within the first region of the lower insulating layer. ### Claim 3 (depends on 2) The method as claimed in claim 2, further comprising forming the highly doped regions within the semiconductor resistor by implanting impurity ions into the semiconductor resistor, using the metal resistor as an ion implantation mask, at the same time the impurity ions are being implanted into the active semiconductor plate, using the metal gate electrode as the ion implantation mask. ### Claim 4 (depends on 1) The method as claimed in claim 1, wherein the metal layer is formed from a metal selected from a group consisting of titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN) layer, and tungsten (W). ### Claim 5 (depends on 3) The method as claimed in claim 3, further comprising forming salicide layers on the highly doped regions of the active semiconductor plate and the semiconductor resistor, respectively. ### Claim 6 (depends on 5) The method as claimed in claim 5, further comprising: forming an interlayer insulating layer on the salicide layers; patterning the interlayer insulating layers to form a plurality of via holes to expose the salicide layers, the gate electrode, and the metal resistor; filling the plurality of via holes; and forming metal interconnection lines on the plurality of via holes. ### Claim 7 (depends on 3) The method as claimed in claim 3, further comprising forming spacers covering sidewalls of the metal gate electrode and the metal resistor before implanting the impurity ions. ### Claim 8 (depends on 6) The method of claimed in claim 6, wherein the metal interconnection lines are formed by a damascene process. ### Claim 9 (depends on 6) The method of claimed in claim 6, wherein the metal interconnection lines and plurality of via holes are formed by a dual-damascene process. ### Claim 10 A method of fabricating a semiconductor device, the method comprising: forming a lower insulating layer on a semiconductor substrate; forming a lightly doped semiconductor layer on the lower insulating layer; forming an active semiconductor plate by patterning the lightly doped semiconductor layer within a first region of the lower insulating layer; sequentially forming a dielectric layer and a metal layer on the semiconductor substrate having the active semiconductor plate; forming a metal gate electrode on the active semiconductor plate by sequentially patterning the dielectric layer and the metal layer within the first region of the lower insulating layer; forming a semiconductor resistor by patterning the lightly doped semiconductor layer within a second region of the lower insulating layer at the same time the lightly doped semiconductor layer within the first region of the lower insulating layer are pattern; forming a metal resistor on the semiconductor resistor by sequentially patterning the metal layer and the dielectric layer within the second region of the lower insulating layer at the same time sequentially patterning the metal layer and the dielectric layer within the first region of the lower insulating layer; and forming highly doped regions within the active semiconductor plate by implanting impurity ions into the active semiconductor plate, using the metal gate electrode as an ion implantation mask. ### Claim 11 (depends on 10) The method as claimed in claim 10, wherein the metal layer is formed of a metal selected from a group consisting of titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), and tungsten (W). ### Claim 12 (depends on 10) The method as claimed in claim 10, further comprising forming a semiconductor resistor by patterning the dielectric layer and the lightly doped semiconductor layer within the second region of the lower insulating layer while patterning the metal layer, the dielectric layer, and the lightly doped semiconductor layer within the first region of the lower insulating layer. ### Claim 13 (depends on 10) The method as claimed in claim 10, further comprising forming the highly doped regions within the semiconductor resistor by implanting impurity ions into the semiconductor resistor, using the metal resistor as an ion implantation mask, at the same time the impurity ions are being implanted into the active semiconductor plate, using the metal gate electrode as the ion implantation mask. ### Claim 14 (depends on 13) The method as claimed in claim 13, further comprising forming salicide layers on the highly doped regions of the active semiconductor plate and the semiconductor resistor, respectively. ### Claim 15 (depends on 14) The method as claimed in claim 14, further comprising: forming an interlayer insulating layer on the salicide layers; patterning the interlayer insulating layers to form a plurality of via holes to expose the salicide layers, the gate electrode, and the metal resistor; filling the plurality of via holes; and forming metal interconnection lines on the plurality of via holes. ### Claim 16 (depends on 10) The method as claimed in claim 10, further comprising forming spacers covering sidewalls of the metal gate electrode and the metal resistor before implanting the impurity ions.