# US 7,611,954 B2 · Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,611,954 B2 - Document ID: US7611954B2 - Status: Granted - Kind: B2 - Application number: 11/150,894 - Filed: 2005-06-13 - Published: 2005-10-20 - Granted: 2009-11-03 - Earliest claimed: 2003-07-01 - Assignees: International Business Machines Corporation - Inventors: Gregory G. Freeman; Marwan H. Khater; Francois Pagette - Web page: https://patentgrep.com/patent/US7611954B2 ## CPC - H10D 10/054: {Forming extrinsic base regions on silicon substrate after insulating device isolation in vertical BJTs having single crystalline emitter, collector or base regions} - H10D 10/40: Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)} - H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge. Since the emitter is formed where the dummy pedestal existed, the extrinsic base is also self-aligned to the emitter. The silicon or polysilicon forming the inner extrinsic base extension region can also be grown in the trench with selective or non-selective epitaxy. ## Claims ### Claim 1 A method of fabricating a self-aligned bipolar transistor, the method comprising: forming a first opening to expose a first extrinsic base region; generating a dummy pedestal within the first opening, the dummy pedestal having a surrounding trench, the generating including: depositing a sacrificial layer in the first opening to form a second opening that is smaller than the first opening, the second opening defining a size of the dummy pedestal; depositing a filler material in the second opening; and removing the sacrificial layer and the filler material to generate the dummy pedestal and the trench; forming an extrinsic base extension region in the trench, the extrinsic base extension region connecting the first extrinsic base region to an intrinsic base; removing the dummy pedestal to form an emitter opening; and forming an emitter in the emitter opening. ### Claim 2 (depends on 1) The method of claim 1, wherein the forming the extrinsic base extension region includes providing one of silicon and polysilicon, and wherein the first extrinsic base region includes one of silicon and polysilicon having a different doping concentration than the extrinsic base extension region. ### Claim 3 (depends on 2) The method of claim 2, wherein the extrinsic base extension region has a higher doping concentration than the first polysilicon. ### Claim 4 (depends on 1) The method of claim 1, wherein the emitter forming includes: forming a spacer on a sidewall of the emitter opening; and depositing a third polysilicon in the emitter opening to form the emitter. ### Claim 5 (depends on 1) The method of claim 1, further comprising the following prior to the forming the first opening: depositing a first dielectric layer; depositing the first polysilicon over the first dielectric layer; and depositing a second dielectric layer over the first polysilicon, wherein the first opening is formed to the first dielectric layer. ### Claim 6 (depends on 5) The method of claim 5, wherein the emitter forming further includes removing the first dielectric layer within the first opening. ### Claim 7 (depends on 5) The method of claim 5, further comprising forming a cap for the extrinsic base extension region in the second dielectric layer. ### Claim 8 (depends on 5) The method of claim 5, fun her comprising thermally growing a thermal oxide layer prior to depositing the first dielectric layer; wherein the surrounding trench is formed to the thermal oxide layer; etching the first dielectric layer to form a ledge under the first extrinsic base region; and etching the thermal oxide layer to enlarge the ledge and extend the surrounding trench to the intrinsic base. ### Claim 9 (depends on 1) The method of claim 1, wherein the mask and the first opening are misaligned. ### Claim 10 A method of fabricating a self-aligned bipolar transistor, the method comprising: forming a first opening, using lithography, to expose an outer extrinsic base region; depositing a sacrificial layer in the first opening; forming, using lithography misaligned with the first opening, a dummy pedestal in the sacrificial layer with a surrounding trench in the first opening; forming one of silicon and polysilicon in the trench to form an inner extrinsic base extension region connecting the outer extrinsic base region to an intrinsic base; removing the dummy pedestal to form an emitter opening; and forming an emitter in the emitter opening. ### Claim 11 (depends on 10) The method of claim 10, wherein the outer extrinsic base region has a different doping concentration than the inner extrinsic base extension region.