# US 7,611,952 B2 · Method of manufacturing semiconductor device having side wall spacers

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- Number: US 7,611,952 B2
- Document ID: US7611952B2
- Status: Granted
- Kind: B2
- Application number: 11/330,264
- Filed: 2006-01-12
- Published: 2006-07-20
- Granted: 2009-11-03
- Earliest claimed: 2005-01-14
- Assignees: Yamaha Corporation
- Inventors: Tamito Suzuki
- Web page: https://patentgrep.com/patent/US7611952B2

## CPC

- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Gate insulating films 12A and 12B of different thickness are formed in element openings 16a and 16b in the isolation film 16 of a wafer 10. The gate insulating film 12B is the thinnest gate insulating film. A dummy insulating film having the same thickness as the thinnest gate insulating film 12B is formed in wafer periphery area WP. Gate electrodes 20A and 20B are formed on the gate insulating films 12A and 12B, and thereafter an insulating film is deposited on the wafer surface. The deposited insulating film is dry-etched to form side wall spacers 22a to 22d on side walls of the gate electrodes 20A and 20B. During dry etching, the time when the semiconductor surfaces are exposed in the element opening 16b and area WP is detected as an etching end point by a change in the emission spectrum intensity of etching byproducts.

## Claims

### Claim 1

A semiconductor device manufacture method comprising the steps of:
(a) forming an isolation region surrounding and defining each of a plurality of active regions and each of a plurality of dummy regions of a semiconductor substrate, said active regions being regions for forming transistors, said dummy regions being regions in which no transistors are formed;
(b) forming thin insulating films on said active regions and dummy regions;
(c) forming a gate electrode on the thin insulating films in said active regions;
(d) implanting impurity ions in said active regions by using said gate electrodes as a mask to form shallow source/drain regions;
(e) depositing a spacer insulating film on said semiconductor substrate, said spacer insulating film covering said gate electrodes;
(f) anisotropically etching said spacer insulating film, detecting as an etching end point a time when surfaces of said semiconductor substrate are exposed in said active regions and dummy regions, wherein an area of thin insulating film is increased by forming a thinnest insulating film in the dummy region, and leaving side wall spacers on side walls of each of said gate electrodes; and
(g) implanting impurity ions into said active regions by using said gate electrodes and side wall spacers as a mask to form low resistivity and deep source/drain regions in said active regions.

### Claim 2 (depends on 1)

The semiconductor device manufacture method according to claim 1, wherein said step (f) detects an etching end point through monitoring a change in an emission spectrum intensity of an etching byproduct.

### Claim 3 (depends on 1)

The semiconductor device manufacture method according to claim 1, wherein said step (f) performs over-etching after the etching end point is detected.

### Claim 4 (depends on 1)

The semiconductor device manufacture method according to claim 1, wherein:
said step (b) forms thin insulating films having a plurality of thicknesses in a plurality of active regions and a dummy insulating film having a thickness equivalent to a thinnest thin insulating film in said dummy regions; and
said step (f) detects as the etching end point a time when surfaces of said semiconductor substrate is exposed by etching said thinnest thin insulating film and said dummy insulating film.

### Claim 5 (depends on 1)

The semiconductor device manufacture method according to claim 1, wherein said dummy regions include an area other than chip forming areas of said semiconductor substrate.

### Claim 6 (depends on 1)

The semiconductor device manufacture method according to claim 1, wherein said dummy regions include an area spaced apart from each of said active regions in in-chip area of said semiconductor substrate.

### Claim 7 (depends on 6)

The semiconductor device manufacture method according to claim 6, wherein said dummy regions include a pad forming area disposed in said in-chip area.

### Claim 8 (depends on 1)

The semiconductor device manufacture method according to claim 1, wherein said dummy regions include an area between chip areas of said semiconductor substrate.

### Claim 9 (depends on 1)

The semiconductor device manufacture method according to claim 1, wherein said dummy regions include an area selected in said isolation region.

### Claim 10 (depends on 1)

The semiconductor device manufacture method according to claim 1, wherein said dummy regions include an inter-cell area in an in-chip area of said semiconductor substrate.

### Claim 11 (depends on 1)

The semiconductor device manufacture method according to claim 1, wherein said semiconductor substrate is a silicon substrate and said thin insulating film and spacer insulating film are silicon oxide films.