# US 7,611,951 B2 · Method of fabricating MOS transistor having epitaxial region

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- Number: US 7,611,951 B2
- Document ID: US7611951B2
- Status: Granted
- Kind: B2
- Application number: 11/517,246
- Filed: 2006-09-08
- Published: 2007-03-08
- Granted: 2009-11-03
- Earliest claimed: 2005-09-08
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Tetsuji Ueno; Hwa-Sung Rhee; Ho Lee
- Web page: https://patentgrep.com/patent/US7611951B2

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 30/21: {of electrically active species}
- H10P 30/225: {of a molecular ion, e.g. decaborane}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an epitaxial region disposed in a lower portion of sidewalls of a gate pattern. Provided is a method of manufacturing a MOS transistor having an epitaxial region which improves an epitaxial growth rate and which may have fewer defects. The method of manufacturing a MOS transistor having an epitaxial region may include forming a gate pattern on a semiconductor substrate, forming a first ion implantation region having a first damage profile by implanting first impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask, forming a second ion implantation region having a second damage profile adjacent to the first damage profile by implanting second impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask and partially etching a lower portion of sidewalls of the gate pattern and forming in-situ an epitaxial region on the etched semiconductor substrate.

## Claims

### Claim 1

A method of manufacturing a MOS transistor having an epitaxial region, the method comprising:
forming a gate pattern on a semiconductor substrate;
forming a first ion implantation region having a first damage profile by implanting first impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask;
forming a second ion implantation region having a second damage profile adjacent to the first damage profile by implanting second impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask; and
partially etching a portion of the semiconductor substrate under the gate pattern and forming in-situ an epitaxial region on the etched semiconductor substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein, in the forming of the second ion implantation region, a pre-amorphization implantation (PAI) process for amorphizing a portion of the semiconductor substrate is performed.

### Claim 3 (depends on 2)

The method of claim 2, wherein the forming of the second ion implantation region is for reducing channeling of the second impurity ions.

### Claim 4 (depends on 2)

The method of claim 2, wherein the amorphous portion of the semiconductor substrate at least partially remains in the lower portion of the sidewalls of the gate pattern.

### Claim 5 (depends on 1)

The method of claim 1, wherein a difference between a peak of the first damage profile and a peak of the second damage profile is less than about 10%.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first impurity ions are Ge, and the second impurity ions are one of B, BF2, As, and Sb.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first impurity ions are Ge, and the second impurity ions are BF2.

### Claim 8 (depends on 7)

The method of claim 7, wherein the ion implantation energy of the germanium (Ge) is in a range of about 3 KeV to about 5 KeV and the ion implantation energy of the BF2 is in a range of about 3 KeV to about 4 KeV.

### Claim 9 (depends on 1)

The method of claim 1, wherein a depth of the first ion implantation region is greater than that of the second ion implantation region.

### Claim 10 (depends on 1)

The method of claim 1, wherein the partial etching of the lower portion of sidewalls of the gate pattern on the etched semiconductor substrate and the forming of the epitaxial region on the etched semiconductor substrate are performed in the same chemical vapor deposition (CVD) reaction chamber.

### Claim 11 (depends on 1)

The method of claim 1, wherein, in the partial etching of the lower portion of sidewalls of the gate pattern on the semiconductor substrate, the semiconductor substrate is isotropically etched.

### Claim 12 (depends on 11)

The method of claim 11, wherein a HCl gas is used as an etching gas in the partial etching of the lower portion of sidewalls of the gate pattern on the semiconductor substrate, and the partial etching is performed in a temperature range of about 650° C. to about 800° C.

### Claim 13 (depends on 12)

The method of claim 12, wherein GeH4, SiH4, and SiH2Cl2 (Dichiorosilane, DCS) are mixed with the HCl gas for etching.

### Claim 14 (depends on 1)

The method of claim 1, wherein the first damage profile is substantially equal to the second damage profile.

### Claim 15 (depends on 1)

The method of claim 1, wherein the epitaxial region is formed of silicon germanium (SiGe).

### Claim 16 (depends on 1)

The method of claim 1, wherein the forming of the epitaxial region is performed in a temperature range of about 650° C. to about 800° C. using a source gas comprising silicon germanium (SiGe).

### Claim 17 (depends on 1)

The method of claim 1, wherein the epitaxial region is formed of silicon carbon (SiC).

### Claim 18 (depends on 1)

The method of claim 1, further comprising:
forming a first gate spacer on the sidewalls of the gate pattern after the formation of the gate pattern and before the formation of the first ion implantation region.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
forming a second gate spacer on the sidewalls of the gate pattern after the formation of the second ion implantation region.

### Claim 20 (depends on 1)

The method of claim 1, further comprising:
forming a halo ion implantation region by implanting halo dopants into the semiconductor substrate using the gate pattern as an ion implantation mask before or after the formation of the first ion implantation region and the formation of the second ion implantation region.

### Claim 21 (depends on 1)

The method of claim 1, further comprising:
forming the second ion implantation region for source/drain regions before the partial etching of the lower portion of sidewalls of the gate pattern on the semiconductor substrate.

### Claim 22 (depends on 1)

The method of claim 1, wherein a lattice constant of the epitaxial region is different from that of the semiconductor substrate, and thus a compressive stress or a tensile stress is induced in the semiconductor substrate between the epitaxial region.

### Claim 23 (depends on 1)

The method of claim 1, further comprising:
an annealing process at lower than about 900° C. before the formation of the epitaxial region.