# US 7,611,944 B2 · Integrated circuit fabrication

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- Number: US 7,611,944 B2
- Document ID: US7611944B2
- Status: Granted
- Kind: B2
- Application number: 11/216,477
- Filed: 2005-08-31
- Published: 2006-09-28
- Granted: 2009-11-03
- Earliest claimed: 2005-03-28
- Assignees: Micron Technology, Inc.
- Inventors: Luan C. Tran; John Lee; Zengtao “Tony” Liu; Eric Freeman; Russell Nielsen
- Web page: https://patentgrep.com/patent/US7611944B2

## CPC

- H10P 76/408: {characterised by their sizes, orientations, dispositions, behaviours or shapes}
- H10B 99/00: Subject matter not provided for in other groups of this subclass
- H10P 50/642: {Chemical etching}
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 76/4088: {Processes for improving the resolution of the masks}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- Y10S 438/947: Subphotolithographic processing
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

## Claims

### Claim 1

A method for defining patterns in an integrated circuit, the method comprising:
defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate;
using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer, the features in the lower masking layer including looped ends;
covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking laver;
etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region, the trenches having a trench width; and
wherein the integrated circuit is a flash memory device.

### Claim 2

A method for defining patterns in an integrated circuit, the method comprising:
defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate;
using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer, the features in the lower masking layer including looped ends;
covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer;
etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region, the trenches having a trench width; and
patterning the second photoresist layer in a third region of the substrate.

### Claim 3 (depends on 2)

The method of claim 2, wherein the features in the lower masking layer have a feature size between approximately 30 nm and approximately 100 nm.

### Claim 4 (depends on 2)

The method of claim 2, wherein the features in the lower masking layer have a feature size between approximately 32.5 nm and approximately 65 nm.

### Claim 5 (depends on 2)

The method of claim 2, wherein the substrate includes a component array including a plurality of electrical components, each having a feature size substantially equal to the trench width.

### Claim 6 (depends on 2)

The method of claim 2, wherein defining the features in the first photoresist layer comprises performing photolithography with light having a wavelength chosen from the group consisting of 157 nm, 193 nm, 248 nm or 365 nm.

### Claim 7 (depends on 2)

The method of claim 2, wherein the first and second photoresist layer comprise the same photoresist material.

### Claim 8 (depends on 2)

The method of claim 2, wherein using pitch multiplication comprises:
depositing a spacer material over the features in the first photoresist layer; and
isotropically etching the spacer material.

### Claim 9 (depends on 2)

The method of claim 2, wherein the substrate is an insulator.

### Claim 10 (depends on 2)

The method of claim 2, wherein etching is conducted while the second photoresist layer covers the second region.

### Claim 11 (depends on 2)

The method of claim 2, wherein the first region includes an array region of a memory device, and the third region includes a periphery region of the memory device.

### Claim 12 (depends on 11)

The method of claim 11, wherein the third region includes an interconnect area in the second photoresist layer adjacent the features in the lower masking layer, wherein a metal is subsequently deposited in the interconnect area to provide an electrical connection from the periphery region of the memory device.

### Claim 13

A method for defining patterns in an integrated circuit, the method comprising:
defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate;
using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer, the features in the lower masking layer including looped ends;
covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer;
etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region, the trenches having a trench width, wherein the trenches are formed in an insulating layer of the substrate, and further comprising:
filling the trenches with a metal layer; and
forming a planar surface on the metal layer down to the insulating layer in a damascene process.

### Claim 14

A method of making a plurality of conductive lines in an array, the method comprising:
providing a film stack including a substrate in contact with a plurality of conductive plugs, an insulating film overlying the conductive plugs, a lower mask layer overlying the insulating film, and an array of spacers formed over the lower mask layer;
depositing a sacrificial film over the lower mask layer and the array of spacers;
forming a resist mask over a portion of the sacrificial film, the resist mask defining an opening over the array of spacers, wherein the lower mask layer and the sacrificial film can be etched selectively with respect to the resist mask;
etching the sacrificial film and exposing a portion of the lower mask layer;
etching the lower mask layer and exposing a portion of the insulating film;
etching a plurality of trenches in the exposed portion of the insulating film to expose at least a portion of the conductive plugs;
performing a metal deposition into the plurality of trenches; and
forming a planar surface alternating between the metal and the insulating film in a damascene process.

### Claim 15 (depends on 14)

The method of claim 14, wherein the trenches form an array of overhead bit lines.

### Claim 16 (depends on 14)

The method of claim 14, further comprising removing the spacer array before etching the plurality of trenches.

### Claim 17 (depends on 14)

The method of claim 14, further comprising removing the spacer array, the resist mask and the sacrificial film before etching the plurality of trenches.

### Claim 18 (depends on 14)

The method of claim 14, wherein the array of spacers has a plurality of looped ends, and wherein the resist mask covers the looped ends of the spacer array.

### Claim 19 (depends on 14)

The method of claim 14, wherein the array is a memory array.

### Claim 20 (depends on 14)

The method of claim 14, wherein the array is a logic array.

### Claim 21 (depends on 14)

The method of claim 14, wherein the sacrificial film is an insulating film.

### Claim 22 (depends on 14)

The method of claim 14, wherein the sacrificial film is a bottom antireflective coating.

### Claim 23 (depends on 14)

The method of claim 14, wherein the spacers are selected from the group consisting of silicon oxide, silicon nitride, polycrystalline silicon, and carbon.

### Claim 24 (depends on 14)

The method of claim 14, wherein the spacers are deposited using an atomic layer deposition process.

### Claim 25 (depends on 14)

The method of claim 14, wherein the spacers are deposited at a temperature that is less than approximately 400° C.

### Claim 26 (depends on 14)

The method of claim 14, wherein the spacers have a feature size between approximately 30 nm and approximately 100 nm.

### Claim 27 (depends on 14)

The method of claim 14, wherein the spacers have a feature size between approximately 32.5 nm and approximately 65 nm.

### Claim 28 (depends on 14)

The method of claim 14, wherein the spacers have a feature size substantially equal to a feature size of the conductive plugs.

### Claim 29 (depends on 14)

The method of claim 14, wherein the sacrificial film forms a substantially planar surface over the array of spacers.

### Claim 30

A method of pitch multiplication for damascene features in an integrated circuit, the method comprising:
providing a substrate;
performing a first masking process to define an array of spacer lines over the substrate, the spacer lines separated by a plurality of gaps;
performing a second masking process that blocks a portion of the spacer lines and that defines a plurality of interconnects in a logic region of the integrated circuit;
etching a plurality of trenches in the gaps between the spacer lines except in the blocked portion;
depositing a metal layer to form a plurality of metal lines in the trenches; and
providing a planar surface on the metal layer to isolate the metal lines in the trenches.

### Claim 31 (depends on 30)

The method of claim 30, wherein the spacer lines have a plurality of looped ends, and wherein the looped ends of the spacer lines are blocked.

### Claim 32 (depends on 30)

The method of claim 30, wherein the integrated circuit is a flash memory device.

### Claim 33 (depends on 30)

The method of claim 30, further comprising connecting the interconnects with a periphery region of the integrated circuit.

### Claim 34 (depends on 30)

The method of claim 30, wherein the spacer lines and the gaps have substantially the same width.

### Claim 35 (depends on 30)

The method of claim 30, wherein the spacer lines comprise an oxide material.

### Claim 36

A method of forming integrated circuit components on a substrate, the method comprising:
using a lithographic technique to pattern a first resist layer and define a plurality of lines;
using a pitch multiplication technique to form a pattern of spacers around a region defined by the plurality of lines, wherein the spacers comprise elongate loops having loop ends;
depositing a second resist layer over the loop ends to define a blocked region of the substrate;
selectively etching through the spacers to from a plurality of trenches in the substrate without etching in the blocked regions;
transferring a pattern of the blocked region from the second resist layer to a hard mask layer; and
removing the second resist layer before etching the trenches.

### Claim 37

A method of forming integrated circuit components on a substrate, the method comprising:
using a lithographic technique to pattern a first resist layer and define a plurality of lines;
using a pitch multiplication technique to form a pattern of spacers around a region defined by the plurality of lines, wherein the spacers comprise elongate loops having loop ends;
depositing a second resist layer over the loop ends to define a blocked region of the substrate; and
selectively etching through the spacers to from a plurality of trenches in the substrate without etching in the blocked regions, wherein the second resist layer comprises amorphous carbon.

### Claim 38

A method of forming integrated circuit components on a substrate, the method comprising:
using a lithographic technique to pattern a first resist layer and define a plurality of lines;
using a pitch multiplication technique to form a pattern of spacers around a region defined by the plurality of lines, wherein the spacers comprise elongate loops having loop ends;
depositing a second resist layer over the loop ends to define a blocked region of the substrate;
selectively etching through the spacers to from a plurality of trenches in the substrate without etching in the blocked regions; and
patterning the second resist layer in a peripheral region of the substrate adjacent to an array region, wherein the spacers are formed in the array region of a memory device.

### Claim 39 (depends on 38)

The method of claim 38, wherein the substrate includes an upper insulator.

### Claim 40 (depends on 38)

The method of claim 38, wherein the first and second resist layers comprise the same resist material.

### Claim 41 (depends on 38)

The method of claim 38, wherein the spacers have a feature size between approximately 22 nm and approximately 45 nm.

### Claim 42 (depends on 38)

The method of claim 38, wherein the spacers have a feature size between approximately 30 nm and approximately 100 nm.

### Claim 43 (depends on 42)

The method of claim 42, wherein the spacers have a feature size between approximately 32.5 nm and approximately 65 nm.

### Claim 44 (depends on 38)

The method of claim 38, wherein the spacers have a feature size substantially equal to a feature size of the trenches.

### Claim 45 (depends on 38)

The method of claim 38, further comprising:
depositing a metal layer into and over the trenches; and
planarizing on the metal layer to form a planar surface that alternates between the metal and an insulator.

### Claim 46 (depends on 45)

The method of claim 45, wherein the metal layer is deposited in an electroplating process.

### Claim 47 (depends on 45)

The method of claim 45, wherein the metal layer comprises a conductor selected from the group consisting of copper and nickel.

### Claim 48

A method of forming integrated circuit components on a substrate, the method comprising:
using a lithographic technique to pattern a first resist layer and define a plurality of lines;
using a pitch multiplication technique to form a pattern of spacers around a region defined by the plurality of lines, wherein the spacers comprise elongate loops having loop ends;
depositing a second resist layer over the loop ends to define a blocked region of the substrate; and
selectively etching through the spacers to from a plurality of trenches in the substrate without etching in the blocked regions, wherein the integrated circuit components form a flash memory device.

### Claim 49

A method of forming a memory device that includes an array region and a peripheral region, the method comprising:
defining a plurality of patterned mask loops in the array region, the patterned mask loops being separated from each other by a gap region;
overlying a lithographic mask over a portion of the array region and at least a portion of a peripheral region, wherein the lithographic mask covers at least a portion of the patterned mask loops;
forming a conductive material in a region left exposed by the lithographic mask; and
forming a plurality of contacts over the conductive material, wherein at least one of the plurality of contacts is positioned within the patterned mask loops, and wherein at least one of the plurality of contacts is positioned in the gap region separating the patterned mask loops.

### Claim 50 (depends on 49)

The method of claim 49, wherein the lithographic mask intersects the plurality of patterned mask loops at a right angle.

### Claim 51 (depends on 49)

The method of claim 49, wherein a portion of the plurality of patterned mask loops has a first loop width in a first region, and has a second loop width in a second region, wherein the second loop width is greater than the first loop width.

### Claim 52 (depends on 51)

The method of claim 51, wherein a contact is positioned in the second region.

### Claim 53 (depends on 49)

The method of claim 49, wherein the plurality of patterned mask loops comprise silicon oxide or silicon nitride.

### Claim 54 (depends on 49)

The method of claim 49, further comprising connecting at least a portion of the plurality of contacts to an array of conductive lines.