# US 7,611,929 B2 · Method for fabricating TFT array substrate

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- Number: US 7,611,929 B2
- Document ID: US7611929B2
- Status: Granted
- Kind: B2
- Application number: 11/642,042
- Filed: 2006-12-18
- Published: 2007-06-21
- Granted: 2009-11-03
- Earliest claimed: 2005-12-16
- Assignees: Innolux Display Corp.
- Inventors: Tzu-Min Yan; Chien-Ting Lai
- Web page: https://patentgrep.com/patent/US7611929B2

## CPC

- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An exemplary method for fabricating a thin film transistor (TFT) array substrate includes: providing an insulating substrate; forming a plurality of gate electrodes and a plurality of reflective patterns on the insulating substrate using a first photo-mask process; forming a gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer, and a source/drain metal layer on the insulating substrate having the gate electrodes and the reflective patterns; forming a plurality of source electrodes and a plurality of drain electrodes on the doped amorphous silicon layer; depositing a passivation layer on the source electrodes, the drain electrodes and the gate insulating layer; and forming a pixel electrode on the passivation layer.

## Claims

### Claim 1

A method for fabricating a thin film transistor (TFT) array substrate, the method comprising:
providing an insulating substrate;
forming a gate electrode and a reflective pattern on the insulating substrate using a first photo-mask process;
forming a gate insulating layer, an amorphous silicon and doped amorphous silicon layer, and a source/drain metal layer on the insulating substrate having the gate electrode and the reflective pattern;
forming a source electrode and a drain electrode on the amorphous silicon and doped amorphous silicon layer;
depositing a passivation layer on the source electrode, the drain electrode and the gate insulating layer; and
forming a pixel electrode on the passivation layer, the pixel electrode completely covering the reflective pattern.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein the photo-mask process for forming the gate electrode and the reflective pattern comprises coating a photo-resist layer on the insulating substrate, exposing the photo-resist layer using a slit photo-mask, and developing the exposed photo-resist layer to form a photo-resist pattern.

### Claim 3 (depends on 2)

The method as claimed in claim 2, wherein the slit photo-mask comprises a plurality of shielding regions and a plurality of slit regions, the shielding regions corresponding to the gate electrode, and the slit regions corresponding to the reflective pattern.

### Claim 4 (depends on 1)

The method as claimed in claim 1, wherein the gate electrode comprises a first metal layer and a second metal layer.

### Claim 5 (depends on 4)

The method as claimed in claim 4, wherein the first metal layer is made from a material having high reflectivity.

### Claim 6 (depends on 5)

The method as claimed in claim 5, wherein the first metal layer is made from aluminum (Al), or an alloy of aluminum and neodymium (Nd).

### Claim 7 (depends on 5)

The method as claimed in claim 5, wherein the reflective pattern is made of a same material as that of the first metal layer.

### Claim 8 (depends on 4)

The method as claimed in claim 4, wherein the second metal layer is wade from material including any one or more items selected from the group consisting of molybdenum (Mo), chromium (Cr), and titanium (Ti).