# US 7,610,572 B2 · Semiconductor integrated circuit device with independent power domains

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- Number: US 7,610,572 B2
- Document ID: US7610572B2
- Status: Granted
- Kind: B2
- Application number: 11/447,168
- Filed: 2006-06-06
- Published: 2006-12-28
- Granted: 2009-10-27
- Earliest claimed: 2005-06-07
- Assignees: Renesas Technology Corp.
- Inventors: Yusuke Kanno; Hiroyuki Mizuno; Yoshihiko Yasu; Kenji Hirose; Takahiro Irita
- Web page: https://patentgrep.com/patent/US7610572B2

## CPC

- H10D 84/998: {Input and output buffer/driver structures}
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G11C 11/419: Read-write [R-W] circuits
- H03K 3/0315: {Ring oscillators}
- H03K 3/0375: {provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)}
- H03K 17/16: Modifications for eliminating interference voltages or currents
- H10D 84/907: {CMOS gate arrays}
- H10D 89/10: Integrated device layouts
- H10W 20/43: Layouts of interconnections
- H10W 72/00: Interconnections or connectors in packages
- G06F 2117/04: Clock gating
- H03K 19/0008: {Arrangements for reducing power consumption}
- H03K 19/00346: {Modifications for eliminating interference or parasitic voltages or currents}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 84/981: {Power supply lines}
- H10D 89/00: Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

## Claims

### Claim 1

A semiconductor integrated circuit device formed on one chip comprising:
a first functional block connected to a first power supply and a second power supply;
a second functional block connected to the first power supply and a third power supply and communicating with the first functional block;
a third functional block connected to the first power supply and a fourth power supply and communicating with the first functional block;
a fourth functional block connected to the first power supply and a fifth power supply and communicating with the second functional block;
a fifth functional block connected to the first power supply and a sixth power supply and communicating with the second functional block;
a first power switch shutting down the first functional block;
a second power switch shutting down the second functional block;
a third power switch shutting down the third functional block;
a fourth power switch shutting down the fourth functional block; and
a fifth power switch shutting down the fifth functional block,
wherein the second to sixth power supplies are independently supplied from each other,
wherein the first functional block is shut down by the first switch only when the second to fifth functional blocks are shut down,
wherein the second functional block is shut down by the second switch only when the fourth and fifth functional blocks are shut down,
wherein a signal transmission between the second functional block and the third functional block is performed via the first functional block,
wherein a signal transmission between the fourth functional block and the fifth functional block is performed via the first functional block or the second functional block,
wherein a signal transmission between the fourth functional block and the third functional block is performed via the first functional block,
wherein each of the signal transmission paths from the second functional block to the first functional block, from the third functional block to the first functional block, from the fourth functional block to each of the first and second functional blocks, and from the fifth functional block to each of the first and second functional blocks has an indefinite signal propagation prevention circuit, and
wherein the signal transmissions paths from the first functional block to each of the second to fifth functional blocks, and from the second functional block to each of the fourth and fifth functional blocks have no indefinite signal propagation circuits.

### Claim 2 (depends on 1)

A semiconductor integrated circuit device according to claim 1,
wherein the first functional block is dispersively laid out inside of each of the second to fifth functional blocks,
wherein the first functional block has a plurality of circuit cells that are arranged in a direction perpendicular to power supply wirings in a lowest layer of power supply layers of basic circuit cells, and
wherein a power supply for the first functional block is wired in a meshed shape so that a drop of a power voltage is minimized in the power supplies of the second to fifth functional blocks.

### Claim 3 (depends on 2)

A semiconductor integrated circuit device according to claim 2,
wherein the power supply for the first functional block is provided in common.

### Claim 4 (depends on 1)

A semiconductor integrated circuit device according to claim 1,
wherein the first functional block has a signal relay buffer for wirings of a long distance signal.

### Claim 5 (depends on 1)

A semiconductor integrated circuit device according to claim 1,
wherein the first functional block has a first clock buffer circuit for a distribution of a clock signal.

### Claim 6 (depends on 5)

A semiconductor integrated circuit device according to claim 5,
wherein the first clock buffer outputs a clock signal to a second clock buffer which is provided in another functional block.

### Claim 7 (depends on 1)

A semiconductor integrated circuit device according to claim 1,
wherein the first functional block has a latch circuit for backing up information when the power of another functional block is shut down.