# US 7,610,571 B2 · Method and system for simulating state retention of an RTL design > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,610,571 B2 - Document ID: US7610571B2 - Status: Granted - Kind: B2 - Application number: 11/489,384 - Filed: 2006-07-18 - Published: 2007-10-18 - Granted: 2009-10-27 - Earliest claimed: 2006-04-14 - Assignees: Cadence Design Systems, Inc. - Inventors: Yonghao Chen - Web page: https://patentgrep.com/patent/US7610571B2 ## CPC - G06F 30/33: Design verification, e.g. functional simulation or model checking - G06F 2119/06: Power analysis or power optimisation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain. ## Claims ### Claim 1 A method for simulating a circuit, comprising: receiving a netlist description of the circuit, wherein the netlist description is represented in a register-transfer-level (RTL) design environment; receiving power information specifications of the circuit; identifying one or more power domains of the circuit using the netlist description and the power information specifications; associating the one or more power domains and the power information specifications in the RTL design environment, wherein the one or more power domains are controlled by a set of power control signals through a power manager logic; and using a computer for simulating state retention behavior in response to variations in power applied to a power domain wherein simulating state retention behavior includes: stopping a clock signal that controls sequential elements in the power domain in response to a clock gating signal being asserted; freezing values of the sequential elements in the power domain; and storing the values of the sequential elements. ### Claim 2 (depends on 1) The method of claim 1, wherein identifying one or more power domains comprises: specifying a list of input pins and output pins belonging to the power domain; and specifying names of instances belonging to the power domain. ### Claim 3 (depends on 2) The method of claim 2, further comprising: specifying ground nets for connecting ground pins of the power domain; and specifying power nets for connecting power pins of the power domain. ### Claim 4 (depends on 2) The method of claim 2, further comprising: specifying conditions for the power domain to be turned on/off and specifying a switch for controlling power on/off of the power domain. ### Claim 5 (depends on 1) The method of claim 1, wherein simulating state retention behavior further comprises: restoring values of sequential elements in response to a state restore enable signal being asserted when the power applied is turned on. ### Claim 6 (depends on 1) The method of claim 1, further comprising: simulating state loss behavior in response to power applied to the power domain being turned off. ### Claim 7 (depends on 6) The method of claim 6, wherein simulating state loss behavior comprises: in response to a power switch enable signal being asserted and power being turned off, driving user-specified state loss values to sequential elements in the power domain. ### Claim 8 (depends on 1) The method of claim 1, further comprising: simulating state gain behavior of the power domain in response to power applied to the power domain being turned on. ### Claim 9 (depends on 8) The method of claim 8, wherein simulating state gain behavior comprises: in response to a power switch enable signal not being asserted and power being turned on, removing previously driven user-specified state loss values from corresponding sequential elements in the power domain. ### Claim 10 (depends on 1) The method of claim 1, wherein simulating state retention behavior further comprises: specifying a class of library cells for mapping existing sequential elements of the power domain; and specifying names of the existing sequential elements to be replaced with corresponding state retention sequential elements. ### Claim 11 (depends on 10) The method of claim 10, further comprising: specifying conditions for when a clock of a state retention sequential element is gated for carrying out a save operation; and specifying conditions for when a clock of a state retention sequential element is gated for carrying out a restore operation. ### Claim 12 (depends on 10) The method of claim 10, further comprising: specifying conditions for state retention sequential elements to be saved; and specifying conditions for state retention sequential elements to be restored. ### Claim 13 (depends on 1) The method of claim 1, wherein power information specifications of the circuit comprises at least one of power-related design intents, power-related constraints, and power-related technology information. ### Claim 14 (depends on 1) The method of claim 1, wherein the one or more power domains are described in a hierarchical simulation data structure. ### Claim 15 (depends on 1) The method of claim 1, wherein the one or more power domains include a plurality of power domains with separate power control signals for controlling power variations in separate portions of the circuit. ### Claim 16 A computer program product for simulating a circuit, comprising a medium storing computer programs for execution by one or more computer systems having at least a processing unit, a user interface and a memory, the computer program product comprising: code for receiving a netlist description of the circuit, wherein the netlist description is represented in a register-transfer-level (RTL) design environment; code for receiving power information specifications of the circuit; code for identifying one or more power domains of the circuit using the netlist description and the power information specifications; code for associating the one or more power domains and the power information specifications in the RTL design environment, wherein the one or more power domains are controlled by a set of power control signals through a power manager logic; and code for simulating state retention behavior in response to variations in power applied to a power domain, wherein the code for simulating state retention behavior includes: code for stopping a clock signal that controls sequential elements in the power domain in response to a clock gating signal being asserted; code for freezing values of the sequential elements in the power domain; and code for storing the values of the sequential elements. ### Claim 17 (depends on 16) The computer program product of claim 16, wherein the code for identifying one or more power domains comprises: code for specifying a list of input pins and output pins belonging to the power domain; and code for specifying names of instances belonging to the power domain. ### Claim 18 (depends on 17) The computer program product of claim 17, further comprising: code for specifying ground nets for connecting ground pins of the power domain; and code for specifying power nets for connecting power pins of the power domain. ### Claim 19 (depends on 17) The computer program product of claim 17, further comprising: code for specifying conditions for the power domain to be turned on/off; and code for specifying a switch for controlling power on/off of the power domain. ### Claim 20 (depends on 16) The computer program product of claim 16, wherein the code for simulating state retention behavior further comprises: code for restoring values of sequential elements in response to a state restore enable signal being asserted when the power applied is turned on. ### Claim 21 (depends on 16) The computer program product of claim 16, further comprising: code for simulating state loss behavior in response to power applied to the power domain being turned off. ### Claim 22 (depends on 21) The computer program product of claim 21, wherein the code for simulating state loss behavior comprises: code for driving user-specified state loss values to sequential elements in the power domain in response to a power switch enable signal being asserted and power being turned off. ### Claim 23 (depends on 16) The computer program product of claim 16, further comprising: code for simulating state gain behavior of the power domain in response to power applied to the power domain being turned on. ### Claim 24 (depends on 23) The computer program product of claim 23, wherein the code for simulating state gain behavior comprises: code for removing previously driven user-specified state loss values from corresponding sequential elements in the power domain in response to a power switch enable signal not being asserted and power being turned on. ### Claim 25 (depends on 16) The computer program product of claim 16, wherein the code for simulating state retention behavior further comprises: code for specifying a class of library cells for mapping existing sequential elements of the power domain; and code for specifying names of the existing sequential elements to be replaced with corresponding state retention sequential elements. ### Claim 26 (depends on 25) The computer program product of claim 25, further comprising: code for specifying conditions for when a clock of a state retention sequential element is gated for carrying out a save operation; and code for specifying conditions for when a clock of a state retention sequential element is gated for carrying out a restore operation. ### Claim 27 (depends on 25) The computer program product of claim 25, further comprising: code for specifying conditions for state retention sequential elements to be saved; and code for specifying conditions for state retention sequential elements to be restored. ### Claim 28 (depends on 16) The computer program product of claim 16, wherein power information specifications of the circuit comprises at least one of power-related design intents, power-related constraints, and power-related technology information. ### Claim 29 (depends on 16) The computer program product of claim 16, wherein the one or more power domains are described in a hierarchical simulation data structure. ### Claim 30 (depends on 16) The computer program product of claim 16, wherein the one or more power domains include a plurality of power domains with separate power control signals for controlling power variations in separate portions of the circuit. ### Claim 31 A computer system for simulating a circuit, the computer system including a processor with memory and a computer-readable medium storing computer programs for execution by the computer system, the computer programs comprising: code for receiving a netlist description of the circuit, wherein the netlist description is represented in a register-transfer-level (RTL) design environment; code for receiving power information specifications of the circuit; code for identifying one or more power domains of the circuit using the netlist description and the power information specifications; code for associating the one or more power domains and the power information specifications in the RTL design environment, wherein the one or more power domains are controlled by a set of power control signals through a power manager logic; and code for simulating state retention behavior in response to variations in power applied to a power domain, wherein the code for simulating state retention behavior includes: code for stopping a clock signal that controls sequential elements in the power domain in response to a clock gating signal being asserted; code for freezing values of the sequential elements in the power domain; and code for storing the values of the sequential elements. ### Claim 32 (depends on 31) The computer system of claim 31, wherein the computer programs further include code for simulating state loss behavior in response to power applied to the power domain being turned off, wherein the code for simulating state loss behavior comprises: code for driving user-specified state loss values to sequential elements in the power domain in response to a power switch enable signal being asserted and power being turned off.