# US 7,610,568 B2 · Methods and apparatus for making placement sensitive logic modifications

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,610,568 B2
- Document ID: US7610568B2
- Status: Granted
- Kind: B2
- Application number: 11/550,448
- Filed: 2006-10-18
- Published: 2007-04-26
- Granted: 2009-10-27
- Earliest claimed: 2005-10-20
- Assignees: Agere Systems Inc.
- Inventors: Stephanie L. Alter; Vishwas Rao
- Web page: https://patentgrep.com/patent/US7610568B2

## CPC

- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/30: Circuit design
- G06F 2119/12: Timing analysis or timing optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Methods and apparatus are described for making a placement sensitive engineering change to meet design for test requirements. One of the methods includes placing a set of new flops in an already placed chip design to meet functional requirements of an engineering change. The already placed chip design is pruned to create a set of valid flops and valid scan chains based on a set of pruning rules. A unified flop database is generated containing physical location and connection information for the new flops and the set of valid flops. A change file for the new flops, selected valid flops, and valid scan chains associated with the selected valid flops is generated meeting allocation and placement sensitive signal connection rules. The new flops are connected to the selected valid flops allowing design for test requirements to be met.

## Claims

### Claim 1

A method executed by a chip-design system for making a placement sensitive engineering change to meet design for test requirements, the method comprising:
placing a set of new flops in an already placed chip design to meet functional requirements of an engineering change;
pruning the already placed chip design to create a set of valid flops and valid scan chains based on a set of pruning rules;
generating a unified flop database containing physical location and connection information for the new flops and the set of valid flops;
generating a change file for the new flops, selected valid flops, and valid scan chains associated with the selected valid flops meeting allocation and placement sensitive signal connection rules; and
connecting the new flops to the selected valid flops allowing design for test requirements to be met.

### Claim 2 (depends on 1)

The method of claim 1 wherein the set of pruning rules comprises:
pruning flops and scan chains associated with at least one dedicated isolation data exchange format wrapper flop.

### Claim 3 (depends on 1)

The method of claim 1 wherein the set of pruning rules comprises:
pruning flops and scan chains associated with at least one shared isolation chain.

### Claim 4 (depends on 1)

The method of claim 1 wherein the set of pruning rules comprises:
pruning multi-cycle flops and scan chains.

### Claim 5 (depends on 1)

The method of claim 1 wherein the set of pruning rules comprises:
pruning memory built in self test flops and scan chains.

### Claim 6 (depends on 1)

The method of claim 1 wherein the set of pruning rules comprises:
pruning logic built in self test controller flops and scan chains.

### Claim 7 (depends on 1)

The method of claim 1 wherein the pruning comprises:
collecting a list of flops which form shared isolation wrappers in a shared isolation flop file; and
correcting names of flops in the shared isolation flop file which do not match flop names in an original chip netlist.

### Claim 8 (depends on 7)

The method of claim 7 wherein the pruning further comprises:
parsing a scan definition file to collect scannable flops from floating and ordered groups of flops;
parsing logic built in self test sub-chains to obtain a list of multi-cycle scan chains;
parsing the shard isolation flop file; and
generating a pruned permitted flop list.

### Claim 9 (depends on 8)

The method of claim 8 wherein the generating a unified flop database comprises:
concatenating the pruned permitted flop list with a list of the new flops to produce a combined flop list;
generating connection information for the flops in the combined flop list in a flop connection file;
determining locations for the flops in the combined flop list in a flop location file; and
merging the flop connection file and flop location file to create the unified flop database.

### Claim 10 (depends on 1)

The method of claim 1 wherein the allocation and placement sensitive signal connection rules comprise:
determining that number of available slots in a selected valid scan chain is greater than zero.

### Claim 11 (depends on 1)

The method of claim 1 wherein the allocation and placement sensitive signal connection rules comprise:
determining that a flop selected from the already placed chip design is closest in distance to a new flop.

### Claim 12

A system for implementing a placement sensitive engineering change to meet design for test requirements the system comprising:
a chip database for storing an already placed chip design;
an engineering change database for storing all engineering change order for the already placed chip design;
a tool database and a programmed processor comprising:
means for placing a set of new flops in the already placed chip design to meet functional requirements of an engineering change;
means for pruning the already placed chip design to create a set of valid flops and valid scan chains based on a set of pruning rules;
means for generating a unified flop database containing physical location and connection information for the new flops and set of valid flops;
means for generating a change file for the new flops, selected valid flops, and valid scan chains associated with the selected valid flops meeting allocation and placement sensitive signal connection rules; and
means for connecting the new flops to the selected valid flops allowing design for test requirements to be met.

### Claim 13 (depends on 12)

The system of claim 12 wherein the programmed processor is a server which has access to the chip database, the engineering change database, and the tool database.

### Claim 14

A computer-readable medium storing a computer program which causes a computer system to perform a method for making a placement sensitive engineering change to meet design for test requirements, the computer-readable medium comprising:
placing a set of new flops in an already placed chip design to meet functional requirements of an engineering change;
pruning the already placed chip design to create a set of valid flops and valid scan chains based on a set of pruning rules;
generating a unified flop database containing physical location and connection information for the new flops and the set of valid flops;
generating a change file for the new flops, selected valid flops, and valid scan chains associated with the selected valid flops meeting allocation and placement sensitive signal connection rules; and
connecting the new flops to the selected valid flops allowing design for test requirements to be met.

### Claim 15 (depends on 14)

The computer-readable medium of claim 14 wherein the set of pruning rules comprises:
pruning flops and scan chains associated with at least one dedicated isolation data exchange format wrapper flop; and
pruning flops and scan chains associated with at least one shared isolation chain.

### Claim 16 (depends on 14)

The computer-readable medium of claim 14 wherein the set of pruning rules comprises:
pruning multi-cycle flops and scan chains.

### Claim 17 (depends on 14)

The computer-readable medium of claim 14 wherein the set of pruning rules comprises:
pruning memory built in self test flops and scan chains; and
pruning logic built in self test controller flops and scan chains.

### Claim 18 (depends on 14)

The computer-readable medium of claim 14 wherein the pruning comprises:
collecting a list of flops which form the shared isolation wrappers in a shared isolation flop file;
correcting the names of flops in the shared isolation flop file which do not match the corresponding flop names in an original chip netlist;
parsing a scan definition file to collect scannable flops from floating and ordered groups of flops;
parsing logic built in self test sub-chains to obtain a list of multi-cycle scan chains;
parsing the shard isolation flop file; and
generating a pruned permitted flop list.

### Claim 19 (depends on 18)

The computer readable medium of claim 18 wherein the generating a unified flop database comprises:
concatenating the pruned permitted flop list with a list of the new flops to produce a combined flop list;
generating connection information for the flops in the combined flop list in a flop connection file;
determining locations for the flops in the combined flop list in a flop location file; and
merging the flop connection file and flop location file to create the unified flop database.

### Claim 20 (depends on 14)

The computer readable medium of claim 14 wherein the allocation and placement sensitive signal connection rules comprise:
determining that number of available slots in a selected valid scan chain is greater than zero; and
determining that a flop selected from the already placed chip design is closest in distance to a new flop.