# US 7,610,544 B2 · Erasure generation in a forward-error-correcting communication system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,610,544 B2 - Document ID: US7610544B2 - Status: Granted - Kind: B2 - Application number: 11/437,282 - Filed: 2006-05-18 - Published: 2006-12-14 - Granted: 2009-10-27 - Earliest claimed: 2005-05-18 - Assignees: Telegent Systems, Inc. - Inventors: Shaori Guo - Web page: https://patentgrep.com/patent/US7610544B2 ## CPC - H04L 1/0052: {Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables} - H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)} - H04L 1/0061: {Error detection codes} - H04L 1/0071: {Use of interleaving (interleaving per se H03M13/27)} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A first data packet is received within an integrated circuit device and stored within a first memory thereof starting at a first address that is determined by the size of one or more previously received data packets. An error descriptor value is updated within a second memory of the integrated circuit device, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies. A multiple-bit error value is generated based, at least in part, on the error descriptor, each bit of the multiple-bit error value corresponding to a respective storage location within a storage row of the first memory. The state of one or more bits within the storage row of the first memory are changed based, at least in part, on the multiple-bit error value. ## Claims ### Claim 1 A method of operation within an integrated circuit device, the method comprising: receiving a first data packet from an external source; storing the first data packet within a first memory starting at a first address that is determined by the size of one or more previously received data packets; updating an error descriptor value within a second memory, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies; generating a multiple-bit error value based, at least in part, on the error descriptor, each bit of the multiple-bit error value corresponding to a respective storage location within a storage row of the first memory; and changing the state of one or more bits within the storage row of the first memory based, at least in part, on the multiple-bit error value. ### Claim 2 (depends on 1) The method of claim 1 wherein receiving a first data packet from an external source comprises receiving the first data packet via a broadcast transmission. ### Claim 3 (depends on 2) The method of claim 2 wherein receiving the first data packet via a broadcast transmission comprises receiving an internet-protocol datagram via a digital video broadcast transmission. ### Claim 4 (depends on 1) The method of claim 1 wherein storing the first data packet within a first memory starting at a first address comprises storing successive bytes of the first data packet within a column of storage locations within the first memory in a column write operation. ### Claim 5 (depends on 4) The method of claim 4 wherein changing the state of one or more bits within the storage row of the first memory comprises outputting contents of the storage row from the first memory in a row read operation. ### Claim 6 (depends on 1) The method of claim 1 wherein updating an error descriptor value within a second memory comprises determining whether a validity field of the error descriptor value indicates that the error descriptor value contains valid error information. ### Claim 7 (depends on 6) The method of claim 6 further comprising: assigning a value to the validity field to indicate that the error descriptor value contains valid error information if the validity field indicates that the error descriptor does not contain valid error information; and assigning the first address within the first memory to the address field if the validity field indicates that the error descriptor does not contain valid error information. ### Claim 8 (depends on 7) The method of claim 7 further comprising assigning a value that indicates a size of the first data packet to the length field if the validity field indicates that the error descriptor does not contain valid error information. ### Claim 9 (depends on 1) The method of claim 1 further comprising: receiving a second data packet; storing the second data packet within the first memory starting at a second address that is determined, at least in part, by the size of the one or more previously received data packets and the size of the first data packet; and updating the error descriptor by assigning an updated length value to the length field, the updated length value being a sum of an existing length value stored within the length field and a value that indicates the size of the second data packet. ### Claim 10 (depends on 9) The method of claim 9 wherein updating the error descriptor by assigning an updated length value to the length field comprises assigning the updated length value to the length field if the second data packet is received immediately after the first data packet and if the second data packet is associated with an error that has a predetermined relationship to the error associated with the first data packet. ### Claim 11 (depends on 1) The method of claim 1 wherein updating the error descriptor includes assigning to the error field one of a plurality of error values that correspond to hierarchical levels of error severity. ### Claim 12 (depends on 1) The method of claim 1 wherein generating the multiple-bit error value based, at least in part, on the error descriptor comprises, evaluating the error descriptor to determine whether the address field and length field define a range of storage locations within the first memory that includes a storage location within the storage row. ### Claim 13 (depends on 12) The method of claim 12 further comprising setting a bit at a first column offset within the storage row to an error-indicating state if the address field and length field define a range of storage locations within the first memory that includes a storage location within the storage row and if the error field indicates a first error type. ### Claim 14 (depends on 13) The method of claim 13 wherein setting a bit at a first column offset within the storage row comprises determining the first column offset based on the address field and length field of the error descriptor. ### Claim 15 (depends on 1) The method of claim 1 wherein changing the state of one or more bits within the storage row of the first memory based, at least in part, on the multiple-bit error value comprises: reading a row of data from the first storage row; performing an error correction operation to generate an updated row of data based on error correction information included within predetermined bit locations within the row of data and based on the multiple-bit error value; and overwriting the row of data within the first storage row with the updated row of data. ### Claim 16 An integrated circuit device comprising: first and second memories; a receiver to receive a first data packet from an external source; and a packet processing circuit to (1) store the first data packet within the first memory starting at a first address that is determined by the size of one or more previously received data packets, and (2) update an error descriptor value within the second memory, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies. ### Claim 17 (depends on 16) The integrated circuit device of claim 16 further comprising an error information generator to generate a multiple-bit error value based, at least in part, on the error descriptor, each bit of the multiple-bit error value corresponding to a respective storage location within a storage row of the first memory. ### Claim 18 (depends on 17) The integrated circuit device of claim 17 wherein the error information generator comprises circuitry to evaluate the error descriptor to determine whether the address field and length field define a range of storage locations within the first memory that includes a storage location within the storage row. ### Claim 19 (depends on 17) The integrated circuit device of claim 17 further comprising an error correction circuit to change the state of one or more bits within the storage row of the first memory based, at least in part, on the multiple-bit error value. ### Claim 20 (depends on 16) The integrated circuit device of claim 16 wherein the receiver comprises a tuner to select a broadcast transmission channel from a range of broadcast transmission channels. ### Claim 21 (depends on 16) The integrated circuit device of claim 16 wherein the packet processing circuit comprises circuitry to (1) assign a value to the validity field to indicate that the error descriptor value contains valid error information if the validity field indicates that the error descriptor does not contain valid error information, and (2) assign the first address within the first memory to the address field if the validity field indicates that the error descriptor does not contain valid error information. ### Claim 22 Computer-readable media having information embodied therein that includes a description of an integrated circuit device, the information including descriptions of: first and second memories; a receiver to receive a first data packet from an external source; and a packet processing circuit to (1) store the first data packet within the first memory starting at a first address that is determined by the size of one or more previously received data packets, and to (2) update an error descriptor value within the second memory, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies. ### Claim 23 An integrated circuit device comprising: first storage means for storing packet data; second storage means for storing error information; means for receiving a first data packet from an external source; means for storing the first data packet within the first storage means starting at a first address that is determined by the size of one or more previously received data packets; and means for updating an error descriptor value within the second storage means, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies.