# US 7,610,539 B2 · Method and apparatus for testing logic circuit designs

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- Number: US 7,610,539 B2
- Document ID: US7610539B2
- Status: Granted
- Kind: B2
- Application number: 12/265,330
- Filed: 2008-11-05
- Published: 2009-05-07
- Granted: 2009-10-27
- Earliest claimed: 2005-10-03
- Assignees: NEC Laboratories America, Inc.
- Inventors: Kedarnath Balakrishnan; Seongmoon Wang; Wenlong Wei; Srimat T. Chakradhar
- Web page: https://patentgrep.com/patent/US7610539B2

## CPC

- G01R 31/31921: {using compression techniques, e.g. patterns sequencer}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

## Claims

### Claim 1

A logic testing system comprising:
a plurality of test pattern generators, each test pattern generator in said plurality having a plurality of stages and configured to generate test patterns for one or more scan chains; and
a phase shifter comprising a plurality of exclusive OR (XOR) gates and in communication with said one or more scan chains and said plurality of test pattern generators such that at least one stage of each test pattern generator in said plurality of test pattern generators is connected to each XOR gate of said phase shifter,
wherein at least a portion of stages of at least a portion of test pattern generators in said plurality of test pattern generators is seeded.

### Claim 2 (depends on 1)

The logic testing system of claim 1 wherein said at least a portion of test pattern generators that are seeded depends on a number of specified bits in a test pattern.

### Claim 3 (depends on 1)

The logic testing system of claim 1 wherein each test pattern generator in said plurality of test pattern generators is connected to a different clock domain.

### Claim 4 (depends on 1)

The logic testing system of claim 1 wherein at least one of said plurality of test pattern generators further comprises at least one of a linear feedback shift register and a linear hybrid cellular automata.

### Claim 5 (depends on 1)

The logic testing system of claim 1 wherein the number of stages in said plurality depends on a maximum number of specified bits (Smax) in a test pattern with unspecified bits and a margin.

### Claim 6 (depends on 1)

The logic testing system of claim 1 wherein a test pattern generator in said plurality is configured to generate seeds for a group of test cubes.

### Claim 7 (depends on 1)

The logic testing system of claim 1 further comprising a dictionary configured to store a plurality of seeds.

### Claim 8 (depends on 7)

The logic testing system of claim 7 further comprising an index associated with said plurality of seeds.

### Claim 9 (depends on 7)

The logic testing system of claim 7 wherein said dictionary is configured to store a plurality of seeds in memory or combinational logic.