# US 7,610,535 B2 · Boundary scan connector test method capable of fully utilizing test I/O modules

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- Number: US 7,610,535 B2
- Document ID: US7610535B2
- Status: Granted
- Kind: B2
- Application number: 11/747,922
- Filed: 2007-05-14
- Published: 2008-10-30
- Granted: 2009-10-27
- Earliest claimed: 2007-04-24
- Assignees: Function Research Inc.
- Inventors: Yu-Jen Huang; Chih-Hung Lin
- Web page: https://patentgrep.com/patent/US7610535B2

## CPC

- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G01R 31/2815: {Functional tests, e.g. boundary scans, using the normal I/O contacts (contacting devices G01R31/2808; testing digital circuits G01R31/317, G06F11/00)}
- G01R 31/318591: {Tools}
- G06F 2113/18: Chip packaging
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

Read the description file of a PCBA without determining and selecting connectors which might be relevant to boundary scan. The description file of the PCBA determines which pins of the connectors on the PCBA should correspond to the pins of a test I/O module. And use the wiring report generated by an auto test program generator to correspond the pins of the test I/O module to the pins of the connectors which are accessed by boundary scan. Thus the IC of the test I/O module would not have any unused pin between any two consecutive pins wired to the connectors of the PCBA.

## Claims

### Claim 1

A boundary scan connector test method comprising:
accessing a description file of a printed circuit board assembly (PCBA);
setting a boundary scan integrated circuit (IC) on the PCBA to determine pins related to boundary scan on the PCBA;
providing a connector on the PCBA to be electrically connected with a test input/output (I/O) module;
executing an auto test program generator to generate a wiring report; and
after pins on the test I/O module and pins of the connector on the PCBA are electrically connected according to the wiring report, performing a boundary scan for the PCBA through the test I/O module to check if the PCBA is normal.

### Claim 2 (depends on 1)

The method of claim 1 further comprising electrically connecting a plurality of connectors on the PCBA through traces.

### Claim 3

A boundary scan connector test method comprising:
accessing a description file of a printed circuit board assembly (PCBA);
setting a boundary scan integrated circuit (IC) on the PCBA to determine pins related to boundary scan on the PCBA;
providing connectors on the PCBA to be electrically connected with test input/output (I/O) modules of a Joint Test Action Group (JTAG) backplane;
executing an auto test program generator to generate a wiring report and a hardware configuration report;
a backplane controller of the JTAG backplane linking a plurality of test I/O modules on the JTAG backplane according to the hardware configuration report; and
after pins on the linked test I/O modules and pins of the connectors on the PCBA are electrically connected according to the wiring report, performing a boundary scan for the PCBA through the linked test I/O modules to check if the PCBA is normal.

### Claim 4 (depends on 3)

The method of claim 3 further comprising electrically connecting a plurality of connectors on the PCBA through traces.

### Claim 5

A boundary scan connector test method comprising:
accessing a description file of a printed circuit board assembly (PCBA);
setting a boundary scan integrated circuit (IC) on the PCBA to determine pins related to boundary scan on the PCBA;
providing connectors on the PCBA to be electrically connected with test input/output (I/O) modules of Joint Test Action Group (JTAG) backplanes;
executing an auto test program generator to generate a wiring report and a hardware configuration report;
a Multiple Scan Path Linker linking a plurality of JTAG backplanes;
backplane controllers of the linked JTAG backplanes linking a plurality of test I/O modules on the linked JTAG backplanes according to the hardware configuration report; and
after pins on the linked test I/O modules and pins of the connectors on the PCBA are electrically connected according to the wiring report, performing a boundary scan for the PCBA through the linked test I/O modules to check if the PCBA is normal.

### Claim 6 (depends on 5)

The method of claim 5 further comprising electrically connecting a plurality of connectors on the PCBA through traces.