# US 7,610,533 B2 · Semiconductor integrated circuit and method for testing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,610,533 B2 - Document ID: US7610533B2 - Status: Granted - Kind: B2 - Application number: 11/266,406 - Filed: 2005-11-04 - Published: 2006-08-03 - Granted: 2009-10-27 - Earliest claimed: 2005-01-31 - Assignees: Panasonic Corporation - Inventors: Takashi Ishimura; Sadami Takeoka - Web page: https://patentgrep.com/patent/US7610533B2 ## CPC - G01R 31/318575: {Power distribution; Power saving} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation. ## Claims ### Claim 1 A semiconductor integrated circuit comprising: a combinational circuit connected with a plurality of flip flop circuits; the plurality of flip flop circuits for capturing a plurality of output signals from the combinational circuit and for forming at least a scan chain; flip-flop-circuit power source wiring for supplying first power supply voltage to the plurality of flip flop circuits; and combinational-circuit power source wiring for supplying second power supply voltage to the combinational circuit, wherein the flip-flop-circuit power source wiring and the combinational-circuit power source wiring are electrically separate from each other at least during scan testing and provide the first power supply voltage to the plurality of flip flop circuits and the second power supply voltage to the combinational circuit, respectively. ### Claim 2 A semiconductor integrated circuit comprising: a combinational circuit connected with a plurality of flip flop circuits; the plurality of flip flop circuits for capturing a plurality of output signals from the combinational circuit and for forming at least a scan chain; power source wiring for supplying power supply voltage to the plurality of flip flop circuits and the combinational circuit; and a variable power supply circuit for varying the power supply voltage to the power source wiring; wherein the variable power supply circuit supplies lower voltage to the combinational circuit during shift operation for scan testing than during capture operation. ### Claim 3 (depends on 1) The circuit of claim 1, further comprising a variable power supply circuit for varying the first power supply voltage to the flip-flop-circuit power source wiring and the second power supply voltage to the combinational-circuit power source wiring. ### Claim 4 (depends on 1) The circuit of claim 1, wherein during capture operation in which the output signals from the combinational circuit are captured into the plurality of flip flop circuits, the second power supply voltage to the combinational-circuit power source wiring is set to a given voltage, and during shift operation for scan test signals provided in scan testing, in which the plurality of flip flop circuits are serially connected one after another, the second power supply voltage to the combinational-circuit power source wiring is set to a voltage lower than the given voltage. ### Claim 5 (depends on 1) The circuit of claim 1, wherein during capture operation in which the output signals from the combinational circuit are captured into the plurality of flip flop circuits, the first power supply voltage to the flip-flop-circuit power source wiring is set to a given voltage, and during shift operation for scan test signals provided in scan testing, in which the plurality of flip flop circuits are serially connected one after another, the first power supply voltage to the flip-flop-circuit power source wiring is set to a voltage higher than the given voltage. ### Claim 6 (depends on 1, 2) The circuit of claim 1 or 2, further comprising a built-in self-test device for performing a self-test of the combinational circuit. ### Claim 7 (depends on 2) The circuit of claim 2, further comprising: a measuring circuit for measuring a period of restoring time required for variation in the power supply voltage supplied from the power source wiring to be restored to a steady state, and a stop control circuit for stopping supply of a clock signal to the plurality of flip flop circuits during the period of restoring time. ### Claim 8 (depends on 1) The circuit of claim 1, further comprising: a first region, in which a plurality of flip-flop-circuit standard cells are provided; a second region, in which a plurality of combinational-circuit standard cells are provided; the flip-flop-circuit power source wiring for supplying power to the plurality of flip-flop-circuit standard cells that form the first region; and the combinational-circuit power source wiring for supplying power to the plurality of combinational-circuit standard cells that form the second region. ### Claim 9 (depends on 8) The circuit of claim 8, wherein the plurality of flip-flop-circuit standard cells are arranged in rows and the plurality of combinational-circuit standard cells are arranged in rows, the rows of the plurality of flip-flop-circuit standard cells and the rows of the plurality of combinational-circuit standard cells extending in the same direction; and the rows of the plurality of flip-flop-circuit standard cells and the rows of the plurality of combinational-circuit standard cells are arranged alternately. ### Claim 10 (depends on 2) The circuit of claim 2, further comprising a combinational-circuit standard cell which includes a power source cut-off circuit. ### Claim 11 (depends on 1) The circuit of claim 1, further comprising a plurality of standard cells, each of which includes therein: a first power source wiring for supplying power to the plurality of flip flop circuits; and a second power source wiring for supplying power to the combinational circuit, wherein the power supply from the flip-flop-circuit power source wiring to the first power source wiring in each of the plurality of standard cells, and the power supply from the combinational-circuit power source wiring to the second power source wiring in each of the plurality of standard cells are performed independently of each other. ### Claim 12 (depends on 1) A semiconductor integrated circuit testing method for testing the semiconductor integrated circuit of claim 1, the method comprising: the first step of lowering the second power supply voltage to the combinational circuit; the second step of setting scan test data in the plurality of flip flop circuits, after the first step has been performed; the third step of raising the second power supply voltage to the combinational circuit, after the second step has been performed; and the fourth step of operating the combinational circuit, after the third step has been performed. ### Claim 13 (depends on 12) The method of claim 12, wherein in the first step, the second power supply voltage to the combinational circuit is cut off. ### Claim 14 (depends on 7) A semiconductor integrated circuit testing method for testing the semiconductor integrated circuit of claim 7, the method comprising: the first step of lowering the power supply voltage to the combinational circuit; the second step of setting scan test data in the plurality of flip flop circuits, after the first step has been performed; the third step of raising the power supply voltage to the combinational circuit, after the second step has been performed; the fourth step of stopping supply of a clock signal to the plurality of flip flop circuits for a certain period of time, after the third step has been performed; and the fifth step of operating the combinational circuit, after the fourth step has been performed. ### Claim 15 (depends on 3) A semiconductor integrated circuit testing method for testing the semiconductor integrated circuit of claim 3, the method comprising: the first step of lowering the second power supply voltage to the combinational circuit; the second step of setting scan test data in the plurality of flip flop circuits, after the first step has been performed; the third step of raising the second power supply voltage to the combinational circuit, after the second step has been performed; the fourth step of stopping supply of a clock signal to the plurality of flip flop circuits for a certain period of time, after the third step has been performed; and the fifth step of operating the combinational circuit, after the fourth step has been performed. ### Claim 16 (depends on 1) A semiconductor integrated circuit testing method for testing the semiconductor integrated circuit of claim 1, the method comprising: the first step of raising the first power supply voltage to the plurality of flip flop circuits; the second step of setting scan test data in the plurality of flip flop circuits, after the first step has been performed; the third step of lowering the first power supply voltage to the plurality of flip flop circuits, after the second step has been performed; and the fourth step of operating the combinational circuit, after the third step has been performed. ### Claim 17 (depends on 7) A semiconductor integrated circuit testing method for testing the semiconductor integrated circuit of claim 7, the method comprising: the first step of raising the power supply voltage to the plurality of flip flop circuits; the second step of setting scan test data in the plurality of flip flop circuits, after the first step has been performed; the third step of lowering the power supply voltage to the plurality of flip flop circuits, after the second step has been performed; the fourth step of stopping supply of a clock signal to the plurality of flip flop circuits for a certain period of time, after the third step has been performed; and the fifth step of operating the combinational circuit, after the fourth step has been performed. ### Claim 18 A semiconductor integrated circuit comprising; a combinational circuit connected with a plurality of flip flop circuits; the plurality of flip flop circuits for capturing a plurality of output signals from the combinational circuit and for forming at least a scan chain; a flip-flop-circuit power source wiring for supplying first power supply voltage to the plurality of flip flop circuits; and a combinational-circuit power source wiring for supplying second power supply voltage to the combinational circuit, wherein the flip-flop-circuit power source wiring and the combinational-circuit power source wiring are electrically separate from each other and provide the first power supply voltage to the plurality of flip flop circuits and the second power supply voltage to the combinational circuit, respectively, and the first power supply voltage to the plurality of flip flop circuits and the second power supply voltage to the combinational circuit are independently adjustable. ### Claim 19 (depends on 18) The circuit of claim 18, further comprising a variable power supply circuit for varying the first power supply voltage to the flip-flop-circuit power source wiring and the second power supply voltage to the combinational-circuit power source wiring. ### Claim 20 (depends on 18) The circuit of claim 18, wherein during capture operation in which the output signals from the combinational circuit are captured into the plurality of flip flop circuits, the second power supply voltage to the combinational-circuit power source wiring is set to a given voltage, and during shift operation for scan test signals provided in scan testing, in which the plurality of flip flop circuits are serially connected one after another, the second power supply voltage to the combinational-circuit power source wiring is set to a voltage lower than the given voltage. ### Claim 21 (depends on 18) The circuit of claim 18, wherein during capture operation in which the output signals from the combinational circuit are captured into the plurality of flip flop circuits, the first power supply voltage to the flip-flop-circuit power source wiring is set to a given voltage, and during shift operation for scan test signals provided in scan testing, in which the plurality of flip flop circuits are serially connected one after another, the first power supply voltage to the flip-flop-circuit power wiring is set to a voltage higher than the given voltage. ### Claim 22 (depends on 18) The circuit of claim 18, further comprising a built-in self-test device for performing a self-test of the combinational circuit. ### Claim 23 (depends on 18) The circuit of claim 18, further comprising: a measuring circuit for measuring a period of restoring time required for variation in the first power supply voltage supplied to the flip-flop-circuit power source wiring and the second power supply voltage supplied to the combinational-circuit power source wiring to be restored to a steady stage, and a stop control circuit for stopping supply of a clock signal to the plurality of flip flop circuits during the period of restoring time.