# US 7,610,530 B2 · Test data generator, test system and method thereof

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- Number: US 7,610,530 B2
- Document ID: US7610530B2
- Status: Granted
- Kind: B2
- Application number: 11/508,177
- Filed: 2006-08-23
- Published: 2007-03-15
- Granted: 2009-10-27
- Earliest claimed: 2005-08-24
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Jin-Mo Jang; Young-Bu Kim; Du-Sik Yoo; Byung-Wook Ahn
- Web page: https://patentgrep.com/patent/US7610530B2

## CPC

- G01R 31/31713: {Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572)}
- G01R 31/30: Marginal testing, e.g. by varying supply voltage (testing computers during standby operation or idle time G06F11/22)
- G01R 31/31708: {Analysis of signal quality (G01R31/31901 takes precedence; measuring frequencies or analysing frequency spectra per se G01R23/00; measuring non-linear distortion per se G01R23/20)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A test data generator, test system and method thereof are provided. In the example method, parallel test data may be received at a first data rate. The received parallel test data may be converted into serial test data at a second data rate. Noise (e.g., jitter noise, level noise, etc.) may be selectively inserted into the converted serial test data. The noise inserted into the serial test data, which may be configured to operate at a higher data rate than the parallel test data, may allow a device to be tested with higher data-rate test data. The example method may be performed by the example test data generator and/or by the example test system.

## Claims

### Claim 1

A test data generator, comprising:
at least one noise insertion block receiving at least a first test input signal and adding noise to the first test input signal, in response to at least two noise control signals, to generate at least a first test noise signal, the at least one noise insertion block including,
a first noise insertion block receiving the first test input signal and adding the noise to the first test input signal, in response to a first at least one noise control signal, to generate the first test noise signal,
a second noise insertion block receiving a second test input signal and adding noise to the second test input signal, in response to a second at least one noise control signal, to generate a second test noise signal; wherein
the noise added by the at least one noise insertion block includes at least one of jitter noise and level noise.

### Claim 2 (depends on 1)

The test data generator of claim 1, wherein the first and second test input signals are serial digital signals having opposite phases.

### Claim 3 (depends on 1)

The test data generator of claim 1, further comprising:
a higher speed interface (HSI) sample data generator combining parallel test data signals having a first data rate to generate the first and second test input signals having a second data rate.

### Claim 4 (depends on 3)

The test data generator of claim 3, wherein the first data rate is lower than the second data rate.

### Claim 5 (depends on 3)

The test data generator of claim 3. wherein the parallel test data signals having the first data rate are generated at an automatic test equipment (ATE) connected to the test data generator.

### Claim 6 (depends on 1)

The test data generator of claim 1, wherein the first noise insertion block includes:
a first jitter noise insertion block generating the first test noise signal by adjusting a phase of the first test input signal in response to the first at least one noise control signal.

### Claim 7 (depends on 6)

The test data generator of claim 6, wherein the first jitter noise insertion block includes:
a first resistor receiving the first test input signal;
a first capacitor with a first end connected to the first resistor and a second end connected to a first P noise control signal; and
a first operational amplifier including a first input terminal connected to an output terminal of the first operational amplifier and a common node between the first resistor and the first capacitor, and a second input terminal connected to a second P noise control signal, the first operational amplifier configured to output the first test noise signal through the output terminal.

### Claim 8 (depends on 7)

The test data generator of claim 7, wherein the first jitter noise insertion block further includes:
a second capacitor with a first end connected to the output terminal of the first operational amplifier and a second end connected to a third P noise control signal.

### Claim 9 (depends on 8)

The test data generator of claim 8, wherein the second noise insertion block includes:
a second jitter noise insertion block generating a second test noise signal by adjusting a phase of the second test input signal in response to the second at least one noise control signal.

### Claim 10 (depends on 9)

The test data generator of claim 9, wherein the second jitter noise insertion block includes:
a third resistor receiving the second test input signal;
a third capacitor with a first end connected to the third resistor and a second end receiving a first N noise control signal; and
a second operational amplifier having a first input terminal connected to an output terminal of the second operational amplifier and a common node between the third resistor and the third capacitor, a second input terminal receiving a second N noise control signal, wherein the output terminal outputs the second test noise signal.

### Claim 11 (depends on 10)

The test data generator of claim 10, wherein the second jitter noise insertion block further includes:
a fourth capacitor with a first end connected to the output terminal of the second operational amplifier and a second end receiving a third N noise control signal.

### Claim 12 (depends on 10)

The test data generator of claim 10, wherein the second jitter noise insertion block further includes:
a first coupling capacitor with a first end receiving the second test input signal and a second end connected to the third resistor; and
a second coupling capacitor with a first end connected to the output terminal of the second operational amplifier and a second end outputs the second test noise signal.

### Claim 13 (depends on 7)

The test data generator of claim 7, wherein the first jitter noise insertion block further includes:
a first coupling capacitor with a first end connected to the first test input signal and a second end connected to the first resistor; and
a second coupling capacitor with a first end connected to the output terminal of the first operational amplifier and a second end connected to the first test noise signal.

### Claim 14 (depends on 1)

The test data generator of claim 1, wherein the first noise insertion block includes:
a first level noise insertion block generating the first test noise signal by adjusting a voltage level of the first test input signal in response to the first at least one noise control signal.

### Claim 15 (depends on 1)

The test data generator of claim 1, wherein the first level noise insertion block includes:
a second resistor receiving the first test input signal; and
a first variable resistor with a first end connected to the second resistor and a second end connected to a first voltage source, the first variable resistor having a variable resistance value varying in response to a fourth P noise control signal,
and wherein the first test noise signal is output through a common node between the second resistor and the first variable resistor.

### Claim 16 (depends on 15)

The test data generator of claim 15, wherein the first level noise insertion block further includes:
a first coupling capacitor with a first end receiving the first test input signal and a second end connected to the second resistor; and
a second coupling capacitor with a first end connected to a common node between the second resistor and the first variable resistor and a second end outputting the first test noise signal.

### Claim 17 (depends on 16)

The test data generator of claim 16, wherein the second noise insertion block includes a second level noise insertion block generating the second test noise signal by adjusting a voltage level of the second test input signal in response to the second at least one noise control signal.

### Claim 18 (depends on 17)

The test data generator of claim 17, wherein the second level noise insertion block includes:
a fourth resistor receiving the second test input signal; and
a second variable resistor with a first end connected to the fourth resistor and a second end connected to a first voltage source,
wherein the second variable resistor has a resistance value that changes in response to a fourth N noise control signal, and the second test noise signal is output through a common node between the fourth resistor and the second variable resistor.

### Claim 19 (depends on 18)

The test data generator of claim 18, wherein the second level noise insertion block further includes:
a third coupling capacitor with a first end receiving the second test input signal and a second end connected to the fourth resistor, and
a fourth coupling capacitor with a first end connected to a common node between the fourth resistor and the second variable resistor and a second end outputting the second test noise signal.

### Claim 20 (depends on 1)

The test data generator of claim 1, wherein the first noise insertion block includes:
a first jitter noise insertion block outputting a first phase delay signal, the first phase delay signal generated by adjusting a phase of the first test input signal in response to the first at least one noise control signal; and
a first level noise insertion block generating the first test noise signal by adjusting a voltage level of the first phase delay signal in response to the first at least one noise control signal.

### Claim 21 (depends on 20)

The test data generator of claim 20, wherein the second noise insertion block includes:
a second jitter noise insertion block outputting a second phase delay signal generated by adjusting a phase of the second test input signal in response to at least a noise control signal; and
a second level noise insertion block generating the second test noise signal by adjusting a voltage level of the second phase delay signal in response to at least a noise control signal.

### Claim 22

A test system for testing electrical characteristics of a device, comprising:
a sample data generator generating serial test data at a first data rate based on parallel test data having a second data rate and outputting first and second test input signals having the first data rate, the first data rate higher than the second data rate; and
a test data generator receiving the first and second test input signals and generating first and second test noise signals by inserting noise into the first and second test input signals in response to a first and a second at least one noise control signal; wherein
the inserted noise includes at least one of litter noise and level noise.

### Claim 23 (depends on 22)

The test system of claim 22, wherein the sample data generator is a higher speed interface (HSI) sample data generator.

### Claim 24 (depends on 22)

The test system of claim 22, wherein the test data generator generates the first test noise signal by adjusting a phase of the first test input signal and generates the second test noise signal by adjusting a phase of the second test input signal in response to the first at least one noise control signal.

### Claim 25 (depends on 22)

The test system of claim 22, wherein the test data generator generates the first test noise signal by adjusting a voltage level of the first test input signal and generates the second test noise signal by adjusting a voltage level of the second test input signal in response to the second at least one noise control signal.

### Claim 26 (depends on 22)

The test system of claim 22, wherein an automatic test system generates the parallel test data.

### Claim 27 (depends on 22)

The test system of claim 22, wherein the first and second test input signals are digital signals having opposite phases.

### Claim 28

A method of testing a device, comprising:
receiving parallel test data at a first data rate;
converting the received parallel test data into serial test data at a second data rate; and
selectively inserting at least one type of noise into the converted serial test data in response to at least two noise control signals; wherein
the noise includes at least one of jitter noise and level noise.

### Claim 29 (depends on 28)

The method of claim 28, wherein the first data rate is lower than the second data rate.

### Claim 30 (depends on 28)

A test data generator performing the method of claim 28.

### Claim 31 (depends on 28)

A test system performing the method of claim 28.