# US 7,610,524 B2 · Memory with test mode output

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- Number: US 7,610,524 B2
- Document ID: US7610524B2
- Status: Granted
- Kind: B2
- Application number: 11/491,640
- Filed: 2006-07-24
- Published: 2007-07-19
- Granted: 2009-10-27
- Earliest claimed: 2004-08-10
- Assignees: Micron Technology, Inc.
- Inventors: Jeffery W. Janzen
- Web page: https://patentgrep.com/patent/US7610524B2

## CPC

- G11C 29/46: Test trigger logic
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods of operating an apparatus allow a memory to generate a test mode signal to trigger a test, in response to the memory detecting a predetermined command from a system bus.

## Claims

### Claim 1

A method comprising:
receiving, at a memory device, information identifying a command for the memory device to monitor;
loading the information into a register of the memory device during an initialization of the memory;
setting an indicator at a storage location in the memory device, the indicator to enable or disable issuing a test mode signal in response to the memory device detecting the command from a system bus such that the test mode signal provides output from the memory device to an external device to trigger a test of the memory device using the external device.

### Claim 2 (depends on 1)

The method of claim 1, wherein setting an indicator includes setting the indicator to enable issuing the test mode signal as output from the memory device.

### Claim 3 (depends on 1)

The method of claim 1, wherein setting an indicator includes setting the indicator in the register into which the information command is loaded.

### Claim 4 (depends on 1)

The method of claim 1, wherein loading the information into a register of the memory device includes loading the information into a mode register of the memory device.

### Claim 5 (depends on 1)

The method of claim 1, wherein the method further includes loading an address into a second register of the memory device, the address correlated to the information.

### Claim 6 (depends on 5)

The method of claim 5, wherein setting an indicator includes setting the indicator in the register into which the information is loaded and in the second register.

### Claim 7 (depends on 5)

The method of claim 5, wherein loading an address into a second register of the memory includes loading the address into a mode register of the memory device.

### Claim 8 (depends on 1)

The method of claim 1, wherein the command includes a read command.

### Claim 9

A method comprising:
monitoring a system bus in a memory device;
decoding a command acquired from monitoring the system bus;
comparing the command to a stored command in one or more registers of the memory device, the stored command at least in part indicative of a test mode;
determining to issue a test mode signal; and
generating the test mode signal in the memory device such that the test mode signal provides output from the memory device to an external device triggering a test of the memory device using the external device, the test mode signal generated in response to detecting the stored command as the command on the system bus and to determining to issue the test mode signal.

### Claim 10 (depends on 9)

The method of claim 9, wherein the method includes providing the test mode signal as output from the memory device.

### Claim 11 (depends on 9)

The method of claim 9, wherein the method includes generating the test mode signal in response to detecting a predetermined command on the system bus when an indicator in a register of the memory device is set to enable generating the test mode signal.

### Claim 12 (depends on 9)

The method of claim 9, wherein generating a test mode signal includes outputting the test mode signal as a single test mode pulse.

### Claim 13 (depends on 9)

The method of claim 9, wherein generating a test mode signal includes outputting the test mode signal having a pulse width ranging from about 2 nanoseconds to about 5 nanoseconds.

### Claim 14 (depends on 9)

The method of claim 9, wherein generating the test mode signal includes outputting the test mode signal at a calibration pin of the memory device.

### Claim 15 (depends on 14)

The method of claim 14, wherein the method includes disabling calibration before outputting the test mode signal at the calibration pin of the memory device.

### Claim 16 (depends on 9)

The method of claim 9, wherein generating the test mode signal includes outputting the test mode signal at a test mode pin of the memory device.

### Claim 17 (depends on 9)

The method of claim 9, wherein the stored command includes a read command.

### Claim 18 (depends on 9)

The method of claim 9, wherein determining to issue a test mode signal includes determining to issue the test mode signal upon determining that the one or more registers of the memory device are set with data to direct the memory device to ignore a bank address and a column address, the bank address and the column address correlated to the decoded acquired command from monitoring the system bus.

### Claim 19 (depends on 9)

The method of claim 9, wherein the method includes counting each time an output is provided from the memory device in response to generating the test mode signal.

### Claim 20 (depends on 19)

The method of claim 19, wherein the method includes collecting the count and predicting power utilization by the memory device.

### Claim 21

A method comprising:
arranging a set of bits to send to a memory device to load into a register of the memory device such that the arranged set of bits includes data to issue a test mode signal that provides output from the memory device to an external device triggering a test of the memory device, using the external device, in response to the memory device detecting a predetermined command from a system bus; and
outputting the set of bits directed to the memory device during an initialization of the memory device.

### Claim 22 (depends on 21)

The method of claim 21, wherein outputting the set of bits includes outputting the set of bits having data to provide an indication to enable or disable the issuing of the test mode signal from the memory device.

### Claim 23 (depends on 21)

The method of claim 21, wherein outputting the set of bits includes outputting the set of bits having data to identify the predetermined command.

### Claim 24 (depends on 21)

The method of claim 21, wherein arranging a set of bits includes formatting the bits to be loaded into a mode register of the memory device.

### Claim 25 (depends on 21)

The method of claim 21, wherein arranging a set of bits includes formatting the bits to be loaded into a mode register of the memory device to identify a method to provide output from the memory device.

### Claim 26 (depends on 21)

The method of claim 21, wherein arranging a set of bits and outputting the set of bits includes formatting the set of bits into an address and sending the address onto an address bus to the memory device.

### Claim 27 (depends on 21)

The method of claim 21, wherein the predetermined command includes a read command.

### Claim 28

A computer-readable medium having computer-executable instructions for performing operations comprising:
arranging a set of bits to send to a memory device to load into a register of the memory device such that the arranged set of bits includes data to issue a test mode signal that provides output from the memory device to an external device triggering a test of the memory device, using the external device, in response to the memory device detecting a predetermined command from a system bus; and
outputting the set of bits directed to the memory device during an initialization of the memory device.

### Claim 29 (depends on 28)

The computer-readable medium of claim 28, wherein outputting the set of bits includes outputting the set of bits having data to provide an indication to enable or disable the issuing of the test mode signal from the memory device.

### Claim 30 (depends on 28)

The computer-readable medium of claim 28, wherein outputting the set of bits includes outputting the set of bits having data to identify the predetermined command.

### Claim 31 (depends on 28)

The computer-readable medium of claim 28, wherein arranging a set of bits includes formatting the bits to be loaded into a mode register of the memory device.

### Claim 32 (depends on 28)

The computer-readable medium of claim 28, wherein arranging a set of bits and outputting the set of bits includes formatting the set of bits into an address and transmitting the address onto an address bus to the memory device.

### Claim 33 (depends on 28)

The method of claim 28, wherein the predetermined command includes a read command.

### Claim 34

A computer-readable medium having computer-executable instructions stored thereon for performing operations comprising:
controlling a memory device to issue a test mode signal from the memory device to an external device to trigger a test of the memory device using the external device, the memory device configured to issue the test mode signal in response to the memory device detecting a predetermined command from a system bus, wherein controlling the memory device includes using a data structure having a field containing data representing information operable with instructions to issue the test mode signal from the memory device to trigger the test of the memory device in response to the memory device detecting the predetermined command from the system bus.

### Claim 35 (depends on 34)

The computer-readable medium of claim 34, wherein the field containing data includes data representing an indication to enable or disable issuing the test mode signal from the memory device.

### Claim 36 (depends on 34)

The computer-readable medium of claim 34, wherein the field containing data includes data representing information identifying the predetermined command.

### Claim 37 (depends on 34)

The computer-readable medium of claim 34, wherein the data structure includes a plurality of fields containing data representing information to issue the test mode signal data formatted as an address to propagate on an address bus.

### Claim 38 (depends on 34)

The computer-readable medium of claim 34, wherein the data structure includes:
a first field containing data representing an indication to enable or disable issuing the test mode signal from the memory device; and
a second field containing data representing information identifying the predetermined command.

### Claim 39 (depends on 34)

The method of claim 34, wherein the predetermined command includes a read command.