# US 7,610,522 B2 · Compliance of master-slave modes for low-level debug of serial links

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- Number: US 7,610,522 B2
- Document ID: US7610522B2
- Status: Granted
- Kind: B2
- Application number: 11/322,060
- Filed: 2005-12-28
- Published: 2007-07-19
- Granted: 2009-10-27
- Earliest claimed: 2005-12-28
- Assignees: Intel Corporation
- Inventors: Timothy Frodsham; Zale Schoenborn; Sanjay Dabral; Muraleedhara H. Navada
- Web page: https://patentgrep.com/patent/US7610522B2

## CPC

- G06F 11/221: {to test buses, lines or interfaces, e.g. stuck-at or open line faults}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A condition is detected to cause a component having physical layer circuitry with a transmitter and a receiver to enter a testing state. The transmitter transmits a pre-selected data pattern while comparing data received by the receiver to the pre-selected data pattern during a first phase of the testing state. The transmitter transmits data received by the receiver without comparing the data received by the receiver to the pre-selected data pattern during a second phase of the testing state.

## Claims

### Claim 1

A method comprising:
detecting a condition to cause a component having physical layer circuitry with a transmitter and a receiver to enter a testing state;
causing the transmitter to transmit a pre-selected data pattern while comparing data received by the receiver to the pre-selected data pattern during a first phase of the testing state; and
causing the transmitter to transmit data received by the receiver without comparing the data received by the receiver to the pre-selected data pattern during a second phase of the testing state.

### Claim 2 (depends on 1)

The method of claim 1 wherein the transmitter transmits the pre-selected data pattern over a point-to-point physical link during the first phase of the testing state.

### Claim 3 (depends on 1)

The method of claim 1 wherein the receiver receives data over a point-to-point physical link during the second phase of the testing state.

### Claim 4 (depends on 1)

The method of claim 1 wherein detecting the condition to cause the component having physical layer circuitry to enter the testing state comprises detecting presence of a test instrument connected to a physical link coupled with the physical layer circuitry.

### Claim 5 (depends on 1)

The method of claim 1 wherein detecting the condition to cause the component having physical layer circuitry to enter the testing state comprises detecting assertion of a forced compliance signal.

### Claim 6

An apparatus comprising:
means for detecting a condition to cause a component having physical layer circuitry with a transmitter and a receiver to enter a testing state;
means for causing the transmitter to transmit a pre-selected data pattern while comparing data received by the receiver to the pre-selected data pattern during a first phase of the testing state; and
means for causing the transmitter to transmit data received by the receiver without comparing the data received by the receiver to the pre-selected data pattern during a second phase of the testing state.

### Claim 7 (depends on 6)

The apparatus of claim 6 wherein the transmitter transmits the pre-selected data pattern over a point-to-point physical link during the first phase of the testing state.

### Claim 8 (depends on 6)

The apparatus of claim 6 wherein the receiver receives data over a point-to-point physical link during the second phase of the testing state.

### Claim 9 (depends on 6)

The apparatus of claim 6 wherein the means for detecting the condition to cause the component having physical layer circuitry to enter the testing state comprises means for detecting presence of a test instrument connected to a physical link coupled with the physical layer circuitry.

### Claim 10 (depends on 6)

The apparatus of claim 6 wherein the means for detecting the condition to cause the component having physical layer circuitry to enter the testing state comprises means for detecting assertion of a forced compliance signal.

### Claim 11

A physical layer interface comprising:
a transmission port to transmit data;
a receiving port to receive data;
comparison circuitry; and
control circuitry coupled with the transmission port, with the receiving port, and with the comparison circuitry, the control circuitry to selectively enter a testing state having at least two phases, wherein during the first phase the control circuitry causes the transmission port to transmit a pre-selected data pattern and also to cause the comparison circuitry to compare data received by the receiving port to the pre-selected pattern, and further wherein during the second phase the control circuitry causes the transmission port to transmit data received by the receiving port.

### Claim 12 (depends on 11)

The apparatus of claim 11 wherein the transmission port transmits the pre-selected data pattern over a point-to-point physical link during the first phase of the testing state.

### Claim 13 (depends on 11)

The apparatus of claim 11 wherein the receiving port receives data over a point-to-point physical link during the second phase of the testing state.

### Claim 14 (depends on 11)

The apparatus of claim 11 wherein selectively entering the testing state comprises the control circuit detecting presence of a test instrument connected to a physical link coupled with the physical layer circuitry.

### Claim 15 (depends on 11)

The apparatus of claim 11 wherein selectively entering the testing state comprises detecting assertion of a forced compliance signal.

### Claim 16

A system comprising:
a transmission port to transmit data;
a receiving port to receive data;
a dynamic random access memory;
comparison circuitry; and
control circuitry coupled with the transmission port, with the receiving port, with the comparison circuitry, and with the dynamic random access memory, the control circuitry to selectively enter a testing state having at least two phases, wherein during the first phase the control circuitry causes the transmission port to transmit a pre-selected data pattern and also to cause the comparison circuitry to compare data received by the receiving port to the pre-selected pattern, and further wherein during the second phase the control circuitry causes the transmission port to transmit data received by the receiving port.

### Claim 17 (depends on 16)

The system of claim 16 wherein the transmission port transmits the pre-selected data pattern over a point-to-point physical link during the first phase of the testing state.

### Claim 18 (depends on 16)

The system of claim 16 wherein the receiving port receives data over a point-to-point physical link during the second phase of the testing state.

### Claim 19 (depends on 16)

The system of claim 16 wherein selectively entering the testing state comprises the control circuit detecting presence of a test instrument connected to a physical link coupled with the physical layer circuitry.

### Claim 20 (depends on 16)

The system of claim 16 wherein selectively entering the testing state comprises detecting assertion of a forced compliance signal.