# US 7,610,517 B2 · Microprocessor with trace functionality

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- Number: US 7,610,517 B2
- Document ID: US7610517B2
- Status: Granted
- Kind: B2
- Application number: 11/521,916
- Filed: 2006-09-14
- Published: 2008-05-29
- Granted: 2009-10-27
- Earliest claimed: 2006-09-14
- Assignees: Innovasic, Inc.
- Inventors: Andrew David Alsup
- Web page: https://patentgrep.com/patent/US7610517B2

## CPC

- G06F 11/3636: {by tracing the execution of the program}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A trace function method for microprocessors is provided. The method is operable with a microprocessor comprising an execution unit operable in one or a plurality of contexts. The method comprises: providing a memory coupled to the execution unit, utilizing the memory to store trace data during a trace operation; and providing hardware utilizable during a trace operation to assist in the trace operation.

## Claims

### Claim 1

A method for providing trace functionality for a microprocessor comprising an execution unit, said method comprising:
providing a memory coupled to said execution unit,
utilizing said memory to store trace data during a trace operation;
providing hardware integrated with said microprocessor and utilizable during a trace operation to assist in said trace operation
providing a trace control coupled to said execution unit and to said memory;
providing a breakpoint control coupled to said execution unit, said trace control and said memory;
providing a plurality of sets of programmable registers coupleable to said breakpoint control, and each set comprising a base address register, a data register, a data mask register and a control register;
providing in said trace control a programmable trace control register and a programmable base write address register, said trace control register being programmable to determine one of a plurality of trace functions; and
integrating said trace control, said breakpoint control and said plurality of sets of programmable registers with said execution unit.

### Claim 2 (depends on 1)

A method in accordance with claim 1, comprising:
selecting said plurality of trace functions to include one or more of a call trace, a branch trace and a data trace.

### Claim 3 (depends on 2)

A method in accordance with claim 2, comprising:
storing trace obtained data into a user selectable portion of said memory.

### Claim 4 (depends on 3)

A method in accordance with claim 3, wherein:
said user selectable portion of said memory comprises one of a memory associated with said execution unit or an external trace memory.

### Claim 5 (depends on 4)

A method in accordance with claim 4, comprising:
programming said programmable trace control register to select at least one of a single address trace, a single-shot buffer trace and a circular buffer trace, and wherein said single address trace uses a single word of address for all trace data written out, wherein said single-shot buffer utilizes a programmable length of said trace buffer memory, and wherein said circular buffer trace utilizes a programmable length of said memory portion in which data writes are wrapped.

### Claim 6 (depends on 5)

A method in accordance with claim 5, comprising:
utilizing said programmable trace control register to select one of a data trace and code execution trace.

### Claim 7 (depends on 6)

A method in accordance with claim 6, comprising:
utilizing said programmable trace control register to select a timed trace in which the time of the occurrence of each write to said memory is stored in said memory portion.

### Claim 8 (depends on 2)

A method in accordance with claim 2, comprising:
programming said programmable trace control register to select at least one of a single address trace, a single-shot buffer trace and a circular buffer trace, and wherein said single address trace uses a single word of address for all trace data written out to said memory portion, wherein said single-shot buffer comprises a memory portion of programmable length, and wherein said circular buffer trace utilizes a programmable memory portion length and in which data writes are wrapped over said length.

### Claim 9 (depends on 8)

A method in accordance with claim 8, comprising:
utilizing said programmable trace control register to select one of a data trace and code execution trace.

### Claim 10 (depends on 9)

A method in accordance with claim 9, comprising:
utilizing said programmable trace control register to select a timed trace in which the time of the occurrence of each write to said memory is stored in said memory portion.

### Claim 11 (depends on 1)

A method in accordance with claim 1, comprising:
programming said programmable trace control register to select at least one of a single address trace, a single-shot buffer trace and a circular buffer trace, and wherein said single address trace uses a single word of address of said memory for all trace data written out, wherein said single-shot buffer comprises a programmable length of said memory portion, and wherein said circular buffer trace utilizes a programmable length of said memory portion in which data writes are wrapped.

### Claim 12 (depends on 11)

A method in accordance with claim 11, comprising:
utilizing said programmable trace control register to select one of a data trace and code execution trace.

### Claim 13 (depends on 12)

A method in accordance with claim 12, comprising:
utilizing said programmable trace control register to select a timed trace in which the time of the occurrence of each write to said memory is stored in said memory portion.

### Claim 14

A method for providing trace functionality for a microprocessor comprising an execution unit, said method comprising:
providing a buffer memory coupled to said execution unit, said buffer memory utilized to store trace data during operation of said execution unit;
providing a trace control coupled to said execution unit and to said buffer memory;
providing a breakpoint control coupled to said execution unit, said trace control and said buffer memory;
providing a plurality of sets of programmable registers coupleable to said breakpoint control, and each set comprising a base address register, a data register, a data mask register and a control register;
providing in said trace control a programmable trace control register and a programmable base write address register, said trace control register being programmable to determine one of a plurality of trace functions.

### Claim 15 (depends on 14)

A method in accordance with claim 14, comprising:
selecting said plurality of trace functions to include one or more of a call trace, a branch trace and a data trace.

### Claim 16 (depends on 15)

A method in accordance with claim 15, comprising:
storing trace obtained data into a user selectable trace buffer memory.

### Claim 17 (depends on 16)

A method in accordance with claim 16, wherein:
said user selectable trace buffer memory comprises one of a memory associated with said execution unit or an external trace memory.

### Claim 18 (depends on 17)

A method in accordance with claim 17, comprising:
programming said programmable trace control register to select at least one of a single address trace, a single-shot buffer trace and a circular buffer trace, and wherein said single address trace uses a single word of address for all trace data written out, wherein said single-shot buffer utilizes a programmable length of said trace buffer memory, and wherein said circular buffer trace utilizes a programmable length of said trace buffer memory in which data writes are wrapped.

### Claim 19 (depends on 18)

A method in accordance with claim 18, comprising:
utilizing said programmable trace control register to select one of a data trace and code execution trace.

### Claim 20 (depends on 19)

A method in accordance with claim 19, comprising:
utilizing said programmable trace control register to select a timed trace in which the time of the occurrence of each write to trace buffer memory is stored in said trace buffer memory.

### Claim 21 (depends on 15)

A method in accordance with claim 15, comprising:
programming said programmable trace control register to select at least one of a single address trace, a single-shot buffer trace and a circular buffer trace, and wherein said single address trace uses a single word of address for all trace data written out to a trace buffer memory, wherein said single-shot buffer comprises a trace buffer memory of programmable length, and wherein said circular buffer trace utilizes a programmable trace buffer memory length and in which data writes are wrapped over said length.

### Claim 22 (depends on 21)

A method in accordance with claim 21, comprising:
utilizing said programmable trace control register to select one of a data trace and code execution trace.

### Claim 23 (depends on 22)

A method in accordance with claim 22, comprising:
utilizing said programmable trace control register to select a timed trace in which the time of the occurrence of each write to trace buffer memory is stored in said trace buffer memory.

### Claim 24 (depends on 14)

A method in accordance with claim 14, comprising:
programming said programmable trace control register to select at least one of a single address trace, a single-shot buffer trace and a circular buffer trace, and wherein said single address trace uses a single word of address of a trace buffer memory for all trace data written out, wherein said single-shot buffer comprises a trace buffer memory of programmable length in a memory, and wherein said circular buffer trace utilizes a programmable trace buffer memory length in which data writes are wrapped.

### Claim 25 (depends on 24)

A method in accordance with claim 24, comprising:
utilizing said programmable trace control register to select one of a data trace and code execution trace.

### Claim 26 (depends on 25)

A method in accordance with claim 25, comprising:
utilizing said programmable trace control register to select a timed trace in which the time of the occurrence of each write to trace buffer memory is stored in said trace buffer memory.

### Claim 27 (depends on 14)

A method in accordance with claim 14, comprising:
utilizing said programmable trace control register to select one of a data trace and code execution trace.

### Claim 28 (depends on 14)

A method in accordance with claim 14, comprising:
utilizing said programmable trace control register to select a timed trace in which the time of the occurrence of each write to trace buffer memory is stored in said trace buffer memory.

### Claim 29 (depends on 14)

A method in accordance with claim 14, comprising:
utilizing said programmable trace control register to select one of a data trace and code execution trace.

### Claim 30 (depends on 29)

A method in accordance with claim 29, comprising:
utilizing said programmable trace control register to select a timed trace in which the time of the occurrence of each write to trace buffer memory is stored in said trace buffer memory.

### Claim 31 (depends on 14)

A method in accordance with claim 14, comprising:
utilizing said break point control to programmably select a mode of tracing when context switching occurs in said execution unit.

### Claim 32 (depends on 31)

A method in accordance with claim 31, comprising:
utilizing said break point control to programmably selecting said mode of tracing for a plurality of contexts.

### Claim 33 (depends on 32)

A method in accordance with claim 32, comprising:
selecting said plurality of trace functions to include one or more of a call trace, a branch trace and a data trace.

### Claim 34 (depends on 33)

A method in accordance with claim 33, comprising:
storing trace obtained data into a user selectable trace buffer memory.

### Claim 35 (depends on 34)

A method in accordance with claim 34, wherein:
said user selectable trace buffer memory comprises one of a memory associated with said execution unit or an external trace memory.

### Claim 36 (depends on 35)

A method in accordance with claim 35, comprising:
programming said programmable trace control register to select at least one of a single address trace, a single-shot buffer trace and a circular buffer trace, and wherein said single address trace uses a single word of address for all trace data written out, wherein said single-shot buffer utilizes a programmable length of said trace buffer memory, and wherein said circular buffer trace utilizes a programmable length of said trace buffer memory in which data writes are wrapped.

### Claim 37 (depends on 36)

A method in accordance with claim 36, comprising:
utilizing said programmable trace control register to select one of a data trace and code execution trace.

### Claim 38 (depends on 37)

A method in accordance with claim 37, comprising:
utilizing said programmable trace control register to select a timed trace in which the time of the occurrence of each write to trace buffer memory is stored in said trace buffer memory.

### Claim 39 (depends on 33)

A method in accordance with claim 33, comprising:
programming said programmable trace control register to select at least one of a single address trace, a single-shot buffer trace and a circular buffer trace, and wherein said single address trace uses a single word of address for all trace data written out to a trace buffer memory, wherein said single-shot buffer comprises a trace buffer memory of programmable length, and wherein said circular buffer trace utilizes a programmable trace buffer memory length and in which data writes are wrapped over said length.

### Claim 40 (depends on 39)

A method in accordance with claim 39, comprising:
utilizing said programmable trace control register to select one of a data trace and code execution trace.

### Claim 41 (depends on 40)

A method in accordance with claim 40, comprising:
utilizing said programmable trace control register to select a timed trace in which the time of the occurrence of each write to trace buffer memory is stored in said trace buffer memory.

### Claim 42 (depends on 32)

A method in accordance with claim 32, comprising:
programming said programmable trace control register to select at least one of a single address trace, a single-shot buffer trace and a circular buffer trace, and wherein said single address trace uses a single word of address of a trace buffer memory for all trace data written out, wherein said single-shot buffer comprises a trace buffer memory of programmable length in a memory, and wherein said circular buffer trace utilizes a programmable trace buffer memory length in which data writes are wrapped.

### Claim 43 (depends on 42)

A method in accordance with claim 42, comprising:
utilizing said programmable trace control register to select one of a data trace and code execution trace.

### Claim 44 (depends on 43)

A method in accordance with claim 43, comprising:
utilizing said programmable trace control register to select a timed trace in which the time of the occurrence of each write to trace buffer memory is stored in said trace buffer memory.

### Claim 45 (depends on 32)

A method in accordance with claim 32, comprising:
utilizing said programmable trace control register to select one of a data trace and code execution trace.

### Claim 46 (depends on 32)

A method in accordance with claim 32, comprising:
utilizing said programmable trace control register to select a timed trace in which the time of the occurrence of each write to trace buffer memory is stored in said trace buffer memory.

### Claim 47 (depends on 46)

A method in accordance with claim 46, comprising:
utilizing said programmable trace control register to select one of a data trace and code execution trace.

### Claim 48

A microprocessor, comprising:
an execution unit operable in a plurality of contexts:
a memory coupled to said execution unit, said memory utilized to store trace data during operation of said execution unit;
a trace control coupled to said execution unit and to said memory;
a breakpoint control coupled to said execution unit, said trace control and said memory;
said breakpoint control comprising: a plurality of sets of programmable registers, each set of programmable registers being provided for a corresponding one context of said plurality of contexts and each set comprising a base address register, a data register, a data mask register and a control register;
said trace control comprising a programmable trace control register and a programmable base write address register, said trace control register being programmable to determine one of a plurality of trace functions.

### Claim 49 (depends on 48)

A microprocessor in accordance with claim 48, comprising:
a user selectable portion of said memory for storing trace data.

### Claim 50 (depends on 49)

A microprocessor in accordance with claim 49, wherein:
said user memory comprises one of a memory associated with said execution unit or an external trace memory.