# US 7,610,513 B2 · Debug device for detecting bus transmission and method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,610,513 B2 - Document ID: US7610513B2 - Status: Granted - Kind: B2 - Application number: 11/608,601 - Filed: 2006-12-08 - Published: 2007-12-20 - Granted: 2009-10-27 - Earliest claimed: 2006-06-16 - Assignees: VIA Technologies, Inc. - Inventors: Jing-Rung Wang; Janq-Lih Hsieh - Web page: https://patentgrep.com/patent/US7610513B2 ## CPC - G06F 11/221: {to test buses, lines or interfaces, e.g. stuck-at or open line faults} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract This invention relates to a debug device and method thereof and is applied to detect transmission on a bus in a computer system having a CPU, a north bridge chip and a south bridge chip. The debug device consists of a processing unit, a comparing unit and a recording unit. The processing unit receives a first address signal and a second address signal from the north bridge chip, and correspondingly transmits an index signal and a test data to the north bridge chip. The comparing unit compares the first and the second address signal to generate a comparing signal. And the recording unit records the first and the second address signal and the comparing signal. The north bridge chip connects to the south bridge chip via a bus, and the debug device also connects to the south bridge chip. Therefore the north bridge chip and the debug device transmit to both through the south chip. ## Claims ### Claim 1 A debug device for detecting transmission on a bus, coupled to a computer system comprising a CPU, a north bridge chip, a south bridge chip, wherein said north bridge chip and said south bridge chip are connected through said bus, the debug device comprises: a processing unit, for receiving a first address signal and a second address signal from said north bridge chip and generating an index signal according to said first address signal and delivering said index signal and a test data to said north bridge chip; a comparing unit, for comparing said first address signal and said second address signal to generate a comparing signal; and a recording unit, for recording said first address signal, said second address signal and said comparing signal, wherein said second address signal is generated by said north bridge chip according to said index signal when receiving said index signal. ### Claim 2 (depends on 1) The debug device according to claim 1, wherein said first address signal and said second address signal are delivered to said processing unit through said south bridge chip; said index signal and said test data are delivered to said north bridge chip through said south bridge chip. ### Claim 3 (depends on 2) The debug device according to claim 2, wherein said debug device is connected to said south bridge chip via a PCI bus or a LPC bus. ### Claim 4 (depends on 1) The debug device according to claim 1, wherein said processing unit generates said test data according to said second address signal. ### Claim 5 (depends on 1) The debug device according to claim 1, wherein said north bridge confirms said test data is received. ### Claim 6 (depends on 1) The debug device according to claim 1, wherein said test data is generated in random or a specific way. ### Claim 7 A detection method for detecting transmission on a bus, said computer system comprises a CPU, a north bridge chip and a south bridge chip, wherein said north bridge chip and said south bridge chip are connected through said bus, the detection method comprising: delivering a first address signal from said north bridge chip to said debug device; generating an index signal according to said first address signal and delivering said index signal from said debug device to said north bridge chip; delivering a second address signal from said north bridge chip to said debug device; delivering a test data from said debug device to said north bridge chip; generating a comparing signal according to said first address signal and said second address signal by said debug device; and issuing a retry signal from said debug device to said CPU; wherein said second address signal is generated by said north bridge chip according to said index signal when receiving said index signal. ### Claim 8 (depends on 7) The detection method according to claim 7, wherein said first address signal, said second address signal, said index signal and said test data are transmitted between said north bridge chip and said debug device through said south bridge chip. ### Claim 9 (depends on 7) The detection method according to claim 7, wherein said debug device is connected to said south bridge chip via a PCI bus or a LPC bus. ### Claim 10 (depends on 7) The detection method according to claim 7, said step of delivering said first address signal from said north bridge chip to said debug device comprising: issuing a booting signal from said CPU to said north bridge chip. ### Claim 11 (depends on 10) The detection method according to claim 10, wherein said retry signal enforces said CPU issuing said booting signal. ### Claim 12 (depends on 7) The detection method according to claim 7, said step of generating a comparing signal according to said first address signal and said second address signal by said debug device comprising: recording said first address signal, said second address signal and said comparing signal. ### Claim 13 (depends on 7) The detection method according to claim 7, wherein said first address signal, said second address signal and said comparing signal may be generated in monotonic series. ### Claim 14 (depends on 7) The detection method according to claim 7, said step of delivering said test data from said debug device to said north bridge chip comprising: confirming said data is received by said north bridge chip. ### Claim 15 (depends on 7) The detection method according to claim 7, wherein said test data is generated in random or a specific way. ### Claim 16 (depends on 1) The debug device according to claim 1, wherein said processing unit issues a retry signal to said CPU, and said CPU issuing a booting signal to said north bridge chip, said north bridge chip issuing another first address signal to the processing unit. ### Claim 17 (depends on 16) The debug device according to claim 16, wherein said processing unit generates another index signal according to said another first address signal, and delivers said another index signal to said north bridge chip to detect at which index signal an error occurs. ### Claim 18 (depends on 7) The detection method according to claim 7, wherein when receiving said retry signal, said CPU issuing a booting signal to said north bridge chip, said north bridge chip issuing another first address signal to the processing unit to repeat the detection method as a cycle. ### Claim 19 (depends on 18) The detection method according to claim 18, wherein said processing unit delivers different index signals to said north bridge chip to detect at which index signal an error occurs. ### Claim 20 (depends on 19) The detection method according to claim 19, wherein said different index signals are a series of continuous address signals, and said processing unit detects at which address signal an error occurs.