# US 7,610,504 B2 · Semiconductor integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,610,504 B2 - Document ID: US7610504B2 - Status: Granted - Kind: B2 - Application number: 11/779,084 - Filed: 2007-07-17 - Published: 2007-12-27 - Granted: 2009-10-27 - Earliest claimed: 2004-07-26 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Kohei Oikawa - Web page: https://patentgrep.com/patent/US7610504B2 ## CPC - G06F 1/10: Distribution of clock signals {, e.g. skew} - G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators} - G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the first clock distribution network, and a second phase synchronizer which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the second clock distribution network. The semiconductor integrated circuit has a mode for changing a value of the second power supply voltage to a value which is different from a value of the first power supply voltage. ## Claims ### Claim 1 A semiconductor integrated circuit comprising: a first power supply region supplied with a first power supply voltage, and having a first clock distribution network; a second power supply region supplied with a second power supply voltage, and having a second clock distribution network; a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the first clock distribution network; and a second phase synchronizer which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the second clock distribution network, wherein the semiconductor integrated circuit has a mode for changing a value of the second power supply voltage to a value which is different from a value of the first power supply voltage. ### Claim 2 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein the first and second phase synchronizers are PLL circuits. ### Claim 3 A semiconductor integrated circuit comprising: a first power supply region supplied with a first power supply voltage, and having a first clock distribution network; a second power supply region supplied with a second power supply voltage, and having a second clock distribution network; a phase synchronizer which outputs an output signal obtained by making a phase of a reference clock signal for controlling data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network; and a first delay circuit driven by the second power supply voltage, the first delay circuit delaying the output signal by a first delay time and providing the delayed signal to a second point of the first clock distribution network; and a second delay circuit driven by the first power supply voltage, the second delay circuit delaying the output signal by a second delay time and providing the delayed signal to a first point of the second clock distribution network, wherein the semiconductor integrated circuit has a mode for changing a value of the second power supply voltage to a value which is different from a value of the first power supply voltage. ### Claim 4 (depends on 3) The semiconductor integrated circuit according to claim 3, wherein the first delay time is equal to a delay time from the first point to a second point of the second clock distribution network, and the second delay time is equal to a delay time from the second point to a third point of the first clock distribution network. ### Claim 5 (depends on 3) The semiconductor integrated circuit according to claim 3, further comprising: a divider connected between the phase synchronizer and the second delay circuit; and a third delay circuit connected between the phase synchronizer and the first delay circuit, and having a delay time which is equal to a delay time of the divider. ### Claim 6 (depends on 3) The semiconductor integrated circuit according to claim 3, wherein the phase synchronizer is a PLL circuit. ### Claim 7 A semiconductor integrated circuit comprising: a first power supply region supplied with a first power supply voltage, and having a first clock distribution network; a second power supply region supplied with a second power supply voltage, and having a second clock distribution network; a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the first clock distribution network; and a second phase synchronizer which provides a second output signal obtained by making the phase of the clock signal at a third point of the first clock distribution network coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the second clock distribution network, wherein the semiconductor integrated circuit has a mode for changing a value of the second power supply voltage to a value which is different from a value of the first power supply voltage. ### Claim 8 (depends on 7) The semiconductor integrated circuit according to claim 7, further comprising: a divider connected between the third point of the first clock distribution network and the second phase synchronizer; and a delay circuit connected between the first point of the second clock distribution network and the second phase synchronizer, and having a delay time which is equal to a delay time of the divider. ### Claim 9 (depends on 7) The semiconductor integrated circuit according to claim 7, wherein the second phase synchronizer has a function for delaying the clock signal at the third point of the first clock distribution network by a delay time according to a phase difference between the phase of the clock signal at the third point of the first clock distribution network and the phase of the clock signal at the first point of the second clock distribution network, and outputting the delayed signal as the second output signal. ### Claim 10 (depends on 9) The semiconductor integrated circuit according to claim 9, wherein the delay circuit which generates a delay time is driven by the second power supply voltage. ### Claim 11 (depends on 7) The semiconductor integrated circuit according to claim 7, wherein the second phase synchronizer has a function for delaying the first output signal by a delay time according to the phase difference between the phase of the clock signal at the third point of the first clock distribution network and the phase of the clock signal at the first point of the second clock distribution network, and outputting the delayed signal as the second output signal. ### Claim 12 (depends on 11) The semiconductor integrated circuit according to claim 11, wherein the delay circuit which generates a delay time is driven by the second power supply voltage. ### Claim 13 (depends on 9) The semiconductor integrated circuit according to claim 9, wherein the first phase synchronizer is a PLL circuit, and the second phase synchronizer is a DLL circuit.