# US 7,610,503 B2 · Methods for generating a delayed clock signal > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,610,503 B2 - Document ID: US7610503B2 - Status: Granted - Kind: B2 - Application number: 11/493,427 - Filed: 2006-07-25 - Published: 2006-11-23 - Granted: 2009-10-27 - Earliest claimed: 2003-11-13 - Assignees: Micron Technology, Inc. - Inventors: Leel S. Janzen - Web page: https://patentgrep.com/patent/US7610503B2 ## CPC - G11C 7/1066: {Output synchronization} - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - G06F 1/10: Distribution of clock signals {, e.g. skew} - G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators} - G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories} - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 2207/2254: Calibration - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal. ## Claims ### Claim 1 A method of generating a clock signal, comprising: synchronizing an internal clock signal to an external clock signal; and delaying the internal clock signal different amounts based on a column address strobe latency value to provide the generated clock signal, the different amounts of delay provided by at least two time delays coupled to receive the internal clock signal and having different time delays. ### Claim 2 (depends on 1) The method of claim 1 wherein delaying the internal clock signal different amounts based on a selection value comprises activating one of a plurality of delay circuits coupled to receive the internal clock signal and having a respective time delay, the activated delay circuit providing an output clock signal having the respective delay relative to the internal clock signal for use as the generated clock signal. ### Claim 3 (depends on 2) The method of claim 2 wherein delaying the internal clock signal different amounts based on a selection value comprises selecting one of the plurality of delay circuits to activate based on a column address strobe latency value. ### Claim 4 (depends on 3) The method of claim 3 wherein the plurality of delay circuits comprises a number of delay circuits equal to the number of possible column address strobe latency values. ### Claim 5 A method of generating a clock signal, comprising: synchronizing an internal clock signal to an external clock signal; and activating one of a plurality of delay circuits based on a column address strobe latency value to provide an activated delay circuit, the plurality of delay circuits coupled to receive the internal clock signal and having different time delays, the activated delay circuit providing an output clock signal having a respective delay relative to the internal clock signal for use as the generated clock signal. ### Claim 6 (depends on 5) The method of claim 5 wherein the plurality of delay circuits comprises a number of delay circuits equal to the number of possible column address strobe latency values. ### Claim 7 (depends on 6) The method of claim 6 wherein each of the plurality of delay circuits comprises a programmable delay element. ### Claim 8 (depends on 7) The method of claim 7 wherein the programmable delay elements comprise a delay element programmable by programming antifuses. ### Claim 9 (depends on 8) The method of claim 8 wherein the plurality of delay circuits comprise at least a first and second delay circuit have first and second time delays, respectively, the first time delay greater than the second time delay, the first delay circuit activated for an input clock frequency less than a threshold frequency and the second delay circuit activated for an input clock frequency greater than the threshold frequency. ### Claim 10 A method of generating a clock signal, comprising: synchronizing an internal generated clock signal to an external generated clock signal; and delaying the internal clock signal through one of a plurality of delay circuits to provide the clock signal, each delay circuit have a different delay, the one of the plurality of delay circuits selected according to a column address strobe latency value. ### Claim 11 (depends on 10) The method of claim 10 wherein the plurality of delay circuits comprises a number of delay circuits equal to the number of possible column address strobe latency values. ### Claim 12 (depends on 10) The method of claim 10 wherein the plurality of delay circuits comprise at least a first and second delay circuit have first and second time delays, respectively, the first time delay greater than the second time delay, the first delay circuit activated for an external clock frequency less than a threshold frequency and the second delay circuit activated for an external clock frequency greater than the threshold frequency. ### Claim 13 (depends on 10) The method of claim 10 wherein delaying the internal clock signal through one of a plurality of delay circuits comprises activating one of the plurality of delay circuits, each of the plurality of delay circuits coupled to receive the internal clock signal.