# US 7,610,500 B2 · Link power saving state

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- Number: US 7,610,500 B2
- Document ID: US7610500B2
- Status: Granted
- Kind: B2
- Application number: 11/950,292
- Filed: 2007-12-04
- Published: 2008-04-17
- Granted: 2009-10-27
- Earliest claimed: 2004-05-21
- Assignees: Intel Corporation
- Inventors: Naveen Cherukuri; Jeffrey R. Wilcox; Sanjay Dabral; Phanindra K. Mannava; Aaron T. Spink; David S. Dunning; Tim Frodsham; Theodore Z. Schoenborn
- Web page: https://patentgrep.com/patent/US7610500B2

## CPC

- G06F 1/3209: Monitoring remote activity, e.g. over telephone lines or network connections
- G06F 1/3253: {Power saving in bus}
- H04L 12/12: Arrangements for remote connection or disconnection of substations or of equipment thereof
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.

## Claims

### Claim 1

A system comprising:
a processor having a point-to-point interface port; and
a chipset having a point-to-point interface port;
wherein said processor port and said chipset port are coupled together via a physical interconnect, the physical interconnect comprising two unidirectional links;
wherein the physical interconnect and the ports are to support a low-power state on one of the unidirectional links and are to concurrently support a normal power state on the other link;
wherein exit from the low-power state does not require a physical layer re-initialization sequence.

### Claim 2 (depends on 1)

The system of claim 1, wherein:
the processor includes a memory controller; and
the chipset is an input/output controller.

### Claim 3 (depends on 1)

The system of claim 1, wherein:
the ports and the physical interconnect are further to support exit from the low power state within a configurable wakeup time.

### Claim 4 (depends on 1)

The system of claim 1 further comprising:
a memory system.

### Claim 5 (depends on 4)

The system of claim 4, wherein:
the memory system further comprises a DRAM.

### Claim 6 (depends on 1)

The system of claim 1, wherein:
the processor further comprises an analog activity detector to detect a break from an electrical idle state on one of the links when the link is in the low power state.

### Claim 7 (depends on 6)

The system of claim 6, wherein:
the processor is further to power down analog activity detector when the link is in the normal power state.

### Claim 8 (depends on 1)

The system of claim 1, wherein:
the chipset further comprises an analog activity detector to detect a break from an electrical idle state on one of the links when the link is in the low power state.

### Claim 9 (depends on 8)

The system of claim 8, wherein:
the chipset is further to power down analog activity detector when the link is in the normal power state.