# US 7,610,499 B2 · Apparatus and method for reducing power consumption of a processor by estimating engine load > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,610,499 B2 - Document ID: US7610499B2 - Status: Granted - Kind: B2 - Application number: 11/555,847 - Filed: 2006-11-02 - Published: 2007-09-06 - Granted: 2009-10-27 - Earliest claimed: 2001-01-22 - Assignees: QUALCOMM Incorporated - Inventors: Andrej Zdravkovic - Web page: https://patentgrep.com/patent/US7610499B2 ## CPC - G06F 9/3869: {Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking} - G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode - G06F 1/324: by lowering clock frequency - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A computer system has a processor and a queue for storing instructions for execution by the processor. The processor is capable of being clocked at a plurality of different clock frequencies. In one embodiment, the clocking frequency is determined by estimating a short or long term load associated with the stored instructions. In another embodiment, the clocking frequency is determined by analyzing a set of the stored instructions. ## Claims ### Claim 1 A method for reducing power consumption of at least one processor, the at least one processor is associated with at least one queue for storing instructions, the method comprising: providing a series of instructions stored in the at least one queue; estimating a short or long term load associated with the series of instructions; selecting a clock rate out of a plurality of clocking rates based on in part the estimated short or long term load; and clocking the at least one processor at the selected clock rate. ### Claim 2 (depends on 1) The method of claim 1, wherein the at least one processor is a graphics processor. ### Claim 3 (depends on 1) The method of claim 1, wherein the short term load is associated with the series of instructions stored in the at least one queue on a chip including the at least one processor. ### Claim 4 (depends on 1) The method of claim 1, wherein the long term load is associated with the series of instructions stored in the at least one queue off a chip including the at least one processor. ### Claim 5 (depends on 1) The method of claim 1, wherein the selected clock rate is also based on the current draw of the at least one processor. ### Claim 6 A system for reducing power consumption of at least one processor, the system comprising: at least one queue having stored instructions; a controller that estimates a short or long term load associated with a series of instructions stored in the at least one queue and selects a clock rate for a clock out of a plurality of clocking rates based on in part the estimated short or long term load; and the clock clocking the at least one processor at the selected clock rate. ### Claim 7 (depends on 6) The system of claim 6, wherein the at least one processor is a graphics processor. ### Claim 8 (depends on 6) The system of claim 6, wherein the short term load is associated with the series of instructions stored in the at least one queue on a chip including the at least one processor. ### Claim 9 (depends on 6) The system of claim 6, wherein the long term load is associated with the series of instructions stored in the at least one queue off a chip including the at least one processor. ### Claim 10 (depends on 6) The system of claim 6, wherein the selected clock rate is also based on the current draw of the at least one processor. ### Claim 11 A method for reducing power consumption of at least one processor, the at least one processor is associated with at least one queue storing instructions for execution by the at least one processor, the method comprising: estimating a load by at least analyzing a set of instructions stored in the at least one queue; selecting a clock rate out of a plurality of clocking rates based on in part the estimated load; and clocking the at least one processor at the selected clock rate. ### Claim 12 (depends on 11) The method of claim 11, wherein the analyzing the set of instructions includes determining a moving average of an intensity of instructions in the set of instructions. ### Claim 13 (depends on 11) The method of claim 11, wherein the analyzing the set of instructions includes determining a queue latency of the at least one queue. ### Claim 14 (depends on 11) The method of claim 11, further comprising: grouping the set of instructions into at least one fuzzy set based on the estimated load; outputting a fuzzy variable based on the at least one fuzzy set; and selecting a clock rate out of a plurality of clocking rates based on in part the fuzzy variable. ### Claim 15 (depends on 11) The method of claim 11, wherein the at least one queue is on a chip including the at least one processor. ### Claim 16 A system for reducing power consumption of at least one processor, the system comprising: a clock adjustment device that estimates a load by at least analyzing a set of instructions stored in at least one queue and selects a clock rate for a clock out of a plurality of clocking rates based on in part the estimated load; wherein the clock adjustment device controls the clock such that the at least one processor is clocked at the selected clock rate. ### Claim 17 (depends on 16) The system of claim 16, wherein analyzing the set of instructions includes determining a moving average of an intensity of instructions in the set of instructions. ### Claim 18 (depends on 16) The system of claim 16, wherein the analyzing the set of instructions includes determining a queue latency of the at least one queue. ### Claim 19 (depends on 16) The system of claim 16, further comprising: a fuzzy logic controller grouping the set of instructions into at least one fuzzy set based on the estimated load and outputting a fuzzy variable based on the at least one fuzzy set; and selecting the clock rate for the clock out of a plurality of clocking rates based on in part the fuzzy variable. ### Claim 20 (depends on 16) The system of claim 16, wherein the at least one queue is on a chip including the at least one processor. ### Claim 21 A system for reducing power consumption of at least one processor, the system comprising: means for storing instructions; means for estimating a short or long term load associated with a series of instructions stored in the means for storing instructions and for selecting a clock rate for a clock out of a plurality of clocking rates based on in part the estimated short or long term load; and means for clocking the at least one processor at the selected clock rate.