# US 7,610,497 B2 · Power management system with a bridge logic having analyzers for monitoring data quantity to modify operating clock and voltage of the processor and main memory

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- Number: US 7,610,497 B2
- Document ID: US7610497B2
- Status: Granted
- Kind: B2
- Application number: 11/048,191
- Filed: 2005-02-01
- Published: 2006-08-03
- Granted: 2009-10-27
- Earliest claimed: 2005-02-01
- Assignees: VIA Technologies, Inc.
- Inventors: Ruei-Ling Lin; Jiin Lai; Hung-Yi Kuo
- Web page: https://patentgrep.com/patent/US7610497B2

## CPC

- G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode
- G06F 1/324: by lowering clock frequency
- G06F 1/3243: {Power saving in microcontroller unit}
- G06F 1/3296: by lowering the supply or operating voltage
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A core logic coupled to a main memory of a computer, comprising an analyzer and a power management unit. The analyzer monitors access request traffic load of main memory. The power management unit employs various power performance trade-off activities with the knowledge of the monitored traffic load according to the state machine.

## Claims

### Claim 1

A bridge logic for managing power consumption of a processor and a main memory, wherein the processor accesses the main memory through the bridge logic, the bridge logic comprising:
a first buffer space for temporarily storing data from the processor;
a second buffer space for temporarily storing data from the main memory;
a first analyzer for monitoring data quantity of the first buffer space in a first period of time to determine if the data quantity of the first buffer space exceeds a first threshold value;
a second analyzer for monitoring data quantity of the second buffer space in a second period of time to determine if the data quantity of the second buffer space exceeds a second threshold value; and
a power management unit, coupled to the first analyzer and the second analyzer, for modifying an operating clock and an operating voltage of the processor and an operating clock and an operating voltage of the main memory based on information from the first analyzer and the second analyzer.

### Claim 2 (depends on 1)

The bridge logic of claim 1, wherein the power management unit further increases the operating clock and the operating voltage of the processor, the first analyzer determines that the data quantity of the first buffer space exceeds the first threshold value in the first period of time.

### Claim 3 (depends on 1)

The bridge logic of claim 1, wherein the power management unit further reduces the operating clocks and the operating voltage of the processor, when the first analyzer determines that the data quantity of the first buffer space does not exceed the first threshold value in the first period of time.

### Claim 4 (depends on 1)

The method of claim 1, further comprising decreasing, by the bridge logic, the operating clock and the operating voltage of the processor, or the operating clock and the operating voltage of the main memory, in response of that the data quantity of the buffer does not exceed the threshold value in the period of time.

### Claim 5 (depends on 1)

The method of claim 1, wherein the buffer comprises a first space for temporarily storing data from the processor, and a second space for temporarily storing data from the main memory.

### Claim 6 (depends on 5)

The method of claim 5, further comprising monitoring, by the bridge logic, the first space of the buffer in a first period of time to determine if the data quantity from the processor exceeds a first threshold value, and accordingly modifying the operating clock and the operating voltage of the processor.

### Claim 7 (depends on 5)

The method of claim 5, further comprising monitoring, by the bridge logic, the second space of the buffer in a second period of time to determine if the data quantity from the main memory exceeds a second threshold value, and accordingly modifying the operating clock and the operating voltage of the main memory.

### Claim 8 (depends on 7)

The method of claim 7, further comprising operating the main memory in page mode in response of that the data quantity from the main memory exceeds the second threshold value within the second period of time, and operating the main memory in non-page mode in response of that the data quantity from the main memory does not exceed the second threshold value within the second period of time.

### Claim 9 (depends on 1)

The bridge logic of claim 1, wherein the power management unit further increases the operating clock and the operating voltage of the main memory, when the second analyzer determines that the data quantity of the second buffer space exceeds the second threshold value in the second period of time.

### Claim 10 (depends on 9)

The bridge logic of claim 9, wherein the main memory is operated in page mode.

### Claim 11 (depends on 1)

The bridge logic of claim 1, wherein the power management unit further reduces the operating clock and the operating voltage of the main memory, when the second analyzer determines that the data quantity of the second buffer space does not exceed the second threshold value in the second period of time.

### Claim 12 (depends on 11)

The bridge logic of claim 11, wherein the main memory is operated in non-page mode.

### Claim 13

A computer system for power management, comprising:
a processor;
a main memory;
a bridge logic coupled between the processor and the main memory, wherein the processor accesses the main memory through the bridge logic; and
a southbridge logic coupled to the bridge logic,
wherein the bridge logic comprises:
a first buffer space for temporarily storing data from the processor;
a second buffer space for temporarily storing data from the main memory;
a first analyzer for monitoring data quantity of the first buffer space in a first period of time to determine if the data quantity of the first buffer space exceeds a first threshold value;
a second analyzer for monitoring data quantity of the second buffer space in a second period of time to determine if the data quantity of the second buffer space exceeds a second threshold value; and
a power management unit, coupled to the first analyzer and the second analyzer, for modifying an operating clock and an operating voltage of the processor, and an operating clock and an operating voltage of the main memory.

### Claim 14 (depends on 13)

The computer system of claim 13, wherein the power management unit further increases the operating clock and the operating voltage of the processor, when the first analyzer determines that the data quantity of the first buffer space exceeds the first threshold value in the first period of time.

### Claim 15 (depends on 13)

The computer system of claim 13, wherein the power management unit further reduces the operating clock and the operating voltage of the processor, when the first analyzer determines that the data quantity of the first buffer space does not exceed the first threshold value in the first period of time.

### Claim 16 (depends on 13)

The computer system of claim 13, wherein the power management unit further increases the operating clock and the operating voltage of the main memory, when the second analyzer determines that the data quantity of the second buffer space exceeds the second threshold value in the second period of time.

### Claim 17 (depends on 16)

The computer system of claim 16 wherein the main memory is operated in page mode.

### Claim 18 (depends on 13)

The computer system of claim 13, wherein the power management unit further reduces the operating clock and the operating voltage of the main memory, when the second analyzer determines that the data quantity of the second buffer space does not exceed the second threshold value in the second period of time.

### Claim 19 (depends on 18)

The computer system of claim 18, wherein the main memory is operated in non-page mode.