# US 7,610,466 B2 · Data processing system using independent memory and register operand size specifiers and method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,610,466 B2 - Document ID: US7610466B2 - Status: Granted - Kind: B2 - Application number: 10/657,510 - Filed: 2003-09-05 - Published: 2005-03-10 - Granted: 2009-10-27 - Earliest claimed: 2003-09-05 - Assignees: Freescale Semiconductor, Inc. - Inventors: William C. Moyer - Web page: https://patentgrep.com/patent/US7610466B2 ## CPC - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30014: {with variable precision} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30069: {Instruction skipping instructions, e.g. SKIP} - G06F 9/30109: {having multiple operands in a single register} - G06F 9/30112: {comprising data of variable length} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/30181: {Instruction operation extension or modification} - G06F 9/30192: {according to data descriptor, e.g. dynamic data typing} - G06F 9/325: {for loops, e.g. loop detection or loop counter} - G06F 9/345: of multiple operands or results {(addressing multiple banks G06F12/06)} - G06F 9/3455: {using stride} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum number of vector elements that may be transferred to or from a single register within a register file. Also, the instructions may use a variety of different addressing modes. The memory element size may be specified independently from the register element size such that source and destination sizes may differ within an instruction. With some instructions, a vector stream may be initiated and conditionally enqueued or dequeued. Truncation or rounding fields may be provided such that source data elements may be truncated or rounded when transferred. Also, source data elements may be sign- or unsigned-extended when transferred. ## Claims ### Claim 1 A data processing system comprising: a memory for storing operands; at least one general purpose register; and processor circuitry for executing one or more instructions, a first single instruction of the one or more instructions for transferring data elements between the memory and the at least one general purpose register wherein the first single instruction specifies both a size of data elements in the memory and a size of data elements in the at least one general purpose register, wherein the size of data elements in memory, as specified by the first single instruction, is separate and independent from the size of data elements in the at least one general purpose register, as specified by the first single instruction. ### Claim 2 (depends on 1) The data processing system of claim 1 wherein the first single instruction comprises independent fields for separately storing a first data size specifier for the memory and a second data size specifier for the at least one general purpose register. ### Claim 3 (depends on 1) The data processing system of claim 1 wherein the first single instruction specifies a storage location for defining a first data size specifier for the memory and a second data size specifier for the at least one general purpose register. ### Claim 4 (depends on 3) The data processing system of claim 3 wherein the storage location is any one of a location in the memory and a processor register location external to the memory. ### Claim 5 (depends on 3) The data processing system of claim 3 wherein the storage location is a control register of the data processing system. ### Claim 6 (depends on 3) The data processing system of claim 3 wherein the storage location is a register within the data processing system that arithmetic, logical and shift operations performed by the data processing system utilize. ### Claim 7 (depends on 1) The data processing system of claim 1 wherein the memory further comprises a plurality of multiple data elements to be transferred between the memory and the at least one general purpose register. ### Claim 8 (depends on 7) The data processing system of claim 7 wherein the multiple data elements are contiguous in the memory. ### Claim 9 (depends on 7) The data processing system of claim 7 wherein the multiple data elements are non-contiguous in the memory. ### Claim 10 (depends on 1) The data processing system of claim 1 wherein each of the at least one general purpose register holds multiple data elements. ### Claim 11 (depends on 1) The data processing system of claim 1 wherein each of the at least one general purpose register comprises a scalar register that has a one-dimensional memory map. ### Claim 12 (depends on 1) The data processor of claim 1 wherein when the first single instruction specifies size of a source data element in the memory to be greater than size of a destination data element in the at least one general purpose register, the processor circuitry truncates a portion of the source data element in the memory. ### Claim 13 (depends on 12) The data processor of claim 12 wherein the portion of the source data element in the memory that is truncated is a high order portion of the source data element in the memory. ### Claim 14 (depends on 12) The data processor of claim 12 wherein the portion of the source data element in the memory that is truncated is a low order portion of the source data element in the memory. ### Claim 15 (depends on 1) The data processor of claim 1 wherein when the first single instruction specifies size of a source data element in the memory to be greater than the size of a destination data element in the at least one general purpose register, the processor circuitry rounds a high order portion of the source data element in the memory based on a value of a low order portion of the source data element in the memory. ### Claim 16 (depends on 1) The data processor of claim 1 wherein when the first single instruction specifies size of a source data element in the memory to have a smaller size than a destination data element in the at least one general purpose register, the processor circuitry places predetermined data values in a portion of the destination data element of the at least one general purpose register that is not filled by the source data element from the memory. ### Claim 17 (depends on 16) The data processor of claim 16 wherein the processor circuitry places predetermined data values in the portion of the destination data element of the at least one general purpose register by using zero extension. ### Claim 18 (depends on 16) The data processor of claim 16 wherein the processor circuitry places predetermined data values in the portion of the destination data element of the at least one general purpose register by using sign extension. ### Claim 19 (depends on 16) The data processor of claim 16 wherein the processor circuitry places predetermined data values in the portion of the destination data element of the at least one general purpose register by filling a predetermined bit value in a low order data portion of the destination data element of the at least one general purpose register. ### Claim 20 (depends on 19) The data processor of claim 19 wherein the predetermined bit value is a zero value. ### Claim 21 (depends on 1) The data processor of claim 1 wherein when the first single instruction specifies size of a destination data element in the memory to be less than a size of a source data element in the at least one general purpose register, the processor circuitry truncates a portion of the source data element in the at least one general purpose register. ### Claim 22 (depends on 21) The data processor of claim 21 wherein the processor circuitry truncates a high order portion of the source data element in the at least one general purpose register. ### Claim 23 (depends on 21) The data processor of claim 21 wherein the processor circuitry truncates a 10 low order portion of the source data element in the at least one general purpose register. ### Claim 24 (depends on 1) The data processor of claim 1 wherein when the first single instruction specifies size of a destination data element in the memory to be less than a size of a source data element in the at least one general purpose register, the processor circuitry rounds a high order portion of the source data element in the at least one general purpose register based on a value of a low order portion of the source data element. ### Claim 25 (depends on 1) The data processor of claim 1 wherein when the first single instruction specifies size of a destination data element in the memory to be greater than a size of a source data element in the at least one general purpose register, the processor circuitry places predetermined data values in a portion of the destination data element in the memory that is not filled by the source data element in the at least one general purpose register. ### Claim 26 (depends on 25) The data processor of claim 25 wherein the processor circuitry places the predetermined data values in the portion of the destination data element in the memory that is not filled by using zero extension. ### Claim 27 (depends on 25) The data processor of claim 25 wherein the processor circuitry places the predetermined data values in the portion of the destination data element in the memory that is not filled by using sign extension. ### Claim 28 (depends on 25) The data processor of claim 25 wherein the processor circuitry places the predetermined data values in the portion of the destination data element in the memory that is not filled by placing a predetermined bit value in a low order data portion of the destination data element. ### Claim 29 (depends on 28) The data processor of claim 28 wherein the predetermined bit value is zero. ### Claim 30 A method for loading and storing data elements in a data processing system comprising: providing a memory for storing operands; providing at least one general purpose register; and executing one or more instructions, a first single instruction causing a transfer of data elements between the memory and the at least one general purpose register wherein the first single instruction specifies both a size of data elements in the memory and a size of data elements in the at least one general purpose register, wherein the size of data elements in memory, as specified by the first single instruction, is separate and independent from the size of data elements in the at least one general purpose register, as specified by the first single instruction. ### Claim 31 (depends on 30) The method of claim 30 further comprising: specifying size of data elements by implementing independent fields within the first single instruction, a first field indicating a first data size specifier for the memory and a second field indicating a second data size specifier for the at least one general purpose register. ### Claim 32 (depends on 30) The method of claim 30 further comprising: specifying size of data elements by implementing a predetermined field within the first single instruction, the predetermined field indicating a storage location for defining a first data size specifier for the memory and a second data size specifier for the at least one general purpose register. ### Claim 33 (depends on 30) The method of claim 30 further comprising: implementing the multiple data elements in contiguous storage within the memory. ### Claim 34 (depends on 30) The method of claim 30 further comprising: implementing the multiple data elements in non-contiguous storage within the memory. ### Claim 35 (depends on 30) The method of claim 30 further comprising: truncating a portion of a source data element in the memory when the first single instruction specifies size of the source data element in the memory to be greater than size of a destination data element in the at least one general purpose register. ### Claim 36 (depends on 30) The method of claim 30 further comprising: rounding a high order portion of a source data element in the memory based on a value of a low order portion of the source data element in the memory when the first single instruction specifies size of the source data element in the memory to be greater than a size of a destination data element in the at least one general purpose register. ### Claim 37 (depends on 30) The method of claim 30 further comprising: placing predetermined data values in a portion of a destination data element of the at least one general purpose register that is not filled by a source data element from the memory when the first single instruction specifies a size of the source data element in the memory to have a smaller size than the destination data element in the at least one general purpose register. ### Claim 38 (depends on 30) The method of claim 30 further comprising: truncating a portion of a source data element in the at least one general purpose register when the first single instruction specifies size of a destination data element in the memory to be less than a size of the source data element in the at least one general purpose register. ### Claim 39 (depends on 30) The method of claim 30 further comprising: rounding a high order portion of a source data element in the at least one general purpose register based on a value of a low order portion of the source data element when the first single instruction specifies size of a destination data element in the memory to be less than a size of the source data element in the at least one general purpose register. ### Claim 40 (depends on 30) The method of claim 30 further comprising: placing predetermined data values in a portion of a destination data element in the memory that is not filled by a source data element in the at least one general purpose register when the first single instruction specifies size of the destination data element in the memory to be greater than a size of the source data element in the at least one general purpose register. ### Claim 41 A data processing system comprising a memory and a processor for executing data processing instructions, a first single instruction of the data processing instructions comprises control information that specifies both a size of data elements stored in the memory and a size of data elements stored in at least one storage location in the data processing system external to the memory, wherein the size of data elements in memory, as specified by the first single instruction, is separate and independent from the size of data elements in the at least one storage location, as specified by the first single instruction. ### Claim 42 (depends on 41) The data processing system of claim 41 wherein the control information of the first single instruction of the data processing instructions further comprises independent fields for separately storing a first data size specifier for the memory and a second data size specifier for at least one general purpose register within the data processing system. ### Claim 43 (depends on 41) The data processing system of claim 41 wherein the control information of the first single instruction of the data processing instructions further comprises a field that specifies a storage location within the data processing system for defining a first data size specifier for the memory and a second data size specifier for at least one general purpose register within the data processing system. ### Claim 44 (depends on 41) The data processing system of claim 41 further comprising control circuitry that adjusts data element size when necessary to communicate data when size of data elements stored in the memory differ from size of data elements stored in the at least one storage location in the data processing system external to the memory.